DSPIC30F6014A-30I/PF Microchip Technology Inc., DSPIC30F6014A-30I/PF Datasheet
DSPIC30F6014A-30I/PF
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DSPIC30F6014A-30I/PF Summary of contents
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... Microchip Technology Inc. Data Sheet High-Performance Digital Signal Controllers Preliminary DS70143B ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , microID, MPLAB, PIC, PICmicro, PICSTART, ® 8-bit MCUs ® code hopping EE OQ © 2005 Microchip Technology Inc. ...
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... All DSP instructions are single cycle - Multiply-Accumulate (MAC) operation • Single-cycle ±16 shift © 2005 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... Bytes Instructions dsPIC30F6011A 64 132K 44K dsPIC30F6012A 64 144K 48K dsPIC30F6013A 80 132K 44K dsPIC30F6014A 80 144K 48K DS70143B-page 2 CMOS Technology: • Low-power, high-speed Flash technology • Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low power consumption Output SRAM EEPROM ...
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... SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2005 Microchip Technology Inc. 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6011A 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 ...
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... AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70143B-page 4 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6012A 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 Preliminary © 2005 Microchip Technology Inc. ...
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... SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2005 Microchip Technology Inc dsPIC30F6013A Preliminary EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS ...
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... DD INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70143B-page dsPIC30F6014A Preliminary EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 ...
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... Appendix A: Revision History............................................................................................................................................................. 221 Appendix B: Device Comparisons ..................................................................................................................................................... 223 Appendix C: Migration from dsPIC30F601x to dsPIC30F601xA Devices.......................................................................................... 225 Index .................................................................................................................................................................................................. 227 The Microchip Web Site ..................................................................................................................................................................... 233 Customer Change Notification Service .............................................................................................................................................. 233 Customer Support .............................................................................................................................................................................. 233 Reader Response .............................................................................................................................................................................. 234 Product Identification System ............................................................................................................................................................ 235 © 2005 Microchip Technology Inc. Preliminary DS70143B-page 7 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70143B-page 8 Preliminary © 2005 Microchip Technology Inc. ...
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... Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030). © 2005 Microchip Technology Inc. This document contains specific information for the dsPIC30F6011A/6012A/6013A/6014A Digital Signal Controller (DSC) devices. The dsPIC30F devices ...
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... OSC2/CLKO/RC15 PORTC EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 PORTD C1RX/RF0 C1TX/RF1 U1RX/SDI1/RF2 EMUD3/U1TX/SDI1/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 PORTF C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SS2/CN11/RG9 CSDI/RG12 CSDO/RG13 CSCK/RG14 COFS/RG15 PORTG © 2005 Microchip Technology Inc. ...
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... Oscillator Timing OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect CAN1, 12-bit ADC CAN2 Timers © 2005 Microchip Technology Inc. X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM 16 Address Address Latch Latch RAGU Y AGU PCH PCL ...
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... Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. ST Compare Fault A input (for Compare channels and 4). ST Compare Fault B input (for Compare channels and 8). — Compare outputs 1 through 8. Analog = Analog input O = Output P = Power Preliminary Description © 2005 Microchip Technology Inc. ...
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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2005 Microchip Technology Inc. Buffer Type ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes ...
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... NOTES: DS70143B-page 14 Preliminary © 2005 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. © 2005 Microchip Technology Inc. There are two methods of accessing data stored in program memory: • The upper 32 Kbytes of data space memory can ...
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... The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23-bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. Preliminary © 2005 Microchip Technology Inc. ...
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... AD39 DSP AccA Accumulators AccB PC22 7 0 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2005 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...
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... DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Function W0; Rem W1 W0; Rem W1 W0; Rem W1 W0; Rem W1 W0; Rem W1 Preliminary © 2005 Microchip Technology Inc. ...
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... EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC © 2005 Microchip Technology Inc. The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70143B-page 20 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2005 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. © 2005 Microchip Technology Inc. 2.4.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true, or complement data into the other input ...
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... Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary © 2005 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2005 Microchip Technology Inc. 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70143B-page 24 Preliminary © 2005 Microchip Technology Inc. ...
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... Table 3-1. Note that the program space address is incremented by two between succes- sive program words in order to provide compatibility with data space addressing. © 2005 Microchip Technology Inc. User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE) for all accesses other than TBLRD/TBLWT, which use TBLPAG< ...
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... Program Memory (48K instructions) 017FFE 018000 Reserved (Read ‘0’s) 7FEFFE 7FF000 Data EEPROM (4 Kbytes) 7FFFFE 800000 Reserved 8005BE 8005C0 UNITID (32 instr.) 8005FE 800600 Reserved F7FFFE Device Configuration F80000 Registers F8000E F80010 Reserved FEFFFE FF0000 DEVID (2) FFFFFE © 2005 Microchip Technology Inc. ...
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... Program 0 Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2005 Microchip Technology Inc. Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA ...
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... P<23:16> maps to the destination byte when byte select = 0; The destination byte will always when byte select = 1. 4. TBLWTH: Table Write High (refer to Section 6.0 “Flash Program Memory” for details on Flash Programming TBLRDL.B (Wn<0> TBLRDL.W TBLRDL.B (Wn<0> Preliminary 0 © 2005 Microchip Technology Inc. ...
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... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the dsPIC30F Programmer’s Reference Manual (DS70030) for details on instruction encoding. © 2005 Microchip Technology Inc. TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn<0> ...
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... PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). DS70143B-page 30 Program Space 0x0000 (1) PSVPAG 0x02 8 0x8000 23 15 Address Concatenation 15 23 0xFFFF Preliminary 0x000100 0 0x010000 0x017FFF Data Read © 2005 Microchip Technology Inc. ...
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... MAC class instructions. The data space memory maps are shown in Figure 3-8 and Figure 3-9. © 2005 Microchip Technology Inc. 3.2.2 DATA SPACES The X data space is used by all instructions and sup- ports all Addressing modes. There are separate read and write data buses ...
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... Optionally Mapped into Program Memory 0xFFFF DS70143B-page 32 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 0x1FFE Y Data RAM (Y) 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2005 Microchip Technology Inc. ...
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... SFR Space 0x07FF 0x0801 8 Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2005 Microchip Technology Inc. LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 0x1FFE Y Data RAM (Y) 0x27FE ...
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... For example, the core would recognize that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws+1 for byte operations and Ws+2 for word operations. Preliminary SFR SPACE UNUSED backward compatibility with © 2005 Microchip Technology Inc. ...
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... Additionally, the whole of X data space is addressable using MOV instructions, which support memory direct addressing with a 16-bit address field. © 2005 Microchip Technology Inc. 3.2.6 SOFTWARE STACK The dsPIC DSC devices contain a software stack. W15 is used as the Stack Pointer. ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) SR 0042 CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT ...
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... NOTES: DS70143B-page 38 Preliminary © 2005 Microchip Technology Inc. ...
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... Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2005 Microchip Technology Inc. 4.1.1 FILE REGISTER INSTRUCTIONS Most File register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near data space) ...
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... The only exception to the usage restrictions is for buff- ers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks will be performed on both the lower and upper address boundaries). Preliminary © 2005 Microchip Technology Inc. ...
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... Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2005 Microchip Technology Inc. 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- ister MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
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... If bit-reversed addressing has already been enabled by setting the BREN (XBREV<15>) bit, then a write to the XBREV register should not be immediately followed by bit-reversed an indirect read operation using the W register that has been designated as the bit-reversed pointer. Preliminary N bytes, addressing and bit-reversed © 2005 Microchip Technology Inc. ...
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... BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 4096 2048 1024 512 256 128 © 2005 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Bit-Reversed Address ...
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... NOTES: DS70143B-page 44 Preliminary © 2005 Microchip Technology Inc. ...
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... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2005 Microchip Technology Inc. • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the con- trol and status flags for the processor exceptions ...
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... DCI – Codec Transfer Done LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority * Reserved on dsPIC30F6011A and dsPIC30F6013A because the DCI module is not available on these devices. Preliminary © 2005 Microchip Technology Inc. Interrupt Source 2 C™ Slave Interrupt 2 C Master Interrupt ...
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... Microchip Technology Inc. Note that many of these trap conditions can only be detected when they occur. Consequently, the question- able instruction is allowed to complete prior to trap exception processing ...
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... The processor then loads the priority level for this interrupt into the STATUS register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. Preliminary © 2005 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 ~ ...
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... If the AIVT is not required, the program memory allo- cated to the AIVT may be used for other purposes. AIVT is not a protected section and may be freely programmed by the user. © 2005 Microchip Technology Inc. 5.6 Fast Context Saving A context saving option is available using shadow reg- isters ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 1 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT — — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...
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... NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2005 Microchip Technology Inc. 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 6.6 DD “Programming Operations” for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. Preliminary © 2005 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2005 Microchip Technology Inc. 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... NOPs. ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2005 Microchip Technology Inc. ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70143B-page 56 Preliminary © 2005 Microchip Technology Inc. ...
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... Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. © 2005 Microchip Technology Inc. Control bit WR initiates write operations similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software. They are cleared in hardware at the com- pletion of the write operation ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence Preliminary © 2005 Microchip Technology Inc. ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2005 Microchip Technology Inc. The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... The NVMADR captures last table access address. ; Select data EEPROM for multi word op ; Operate Key to allow program operation ; Block all interrupts with priority <7 for ; next 5 instructions ; Write the 0x55 key ; Write the 0xAA key ; Start write cycle Preliminary © 2005 Microchip Technology Inc. ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. © 2005 Microchip Technology Inc. 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70143B-page 62 Preliminary © 2005 Microchip Technology Inc. ...
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... WR LAT + WR Port Read LAT Read Port © 2005 Microchip Technology Inc. Any bit and its associated data and control registers that are not valid for a particular device will be dis- abled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the ) will be OL device specifications. Output Multiplexers 1 Output Enable 0 1 Output Data Preliminary I/O Cell I/O Pad Input Data © 2005 Microchip Technology Inc. ...
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TABLE 8-1: PORTA REGISTER MAP FOR dsPIC30F6013A/6014A SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 TRISA15 TRISA14 TRISA13 TRISA12 PORTA 02C2 RA15 RA14 RA13 RA12 LATA 02C4 LATA15 LATA14 LATA13 LATA12 Note: PORTA is not ...
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TABLE 8-5: PORTD REGISTER MAP FOR dsPIC30F6011A/6012A SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISD 02D2 — — — — TRISD11 TRISD10 TRISD9 PORTD 02D4 — — — — LATD 02D6 — — — — LATD11 ...
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... CN22IE CNPU1 00C4 CN7PUE CN6PUE CNPU2 00C6 CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields. © 2005 Microchip Technology Inc. Bit 13 Bit 12 Bit 11 Bit 10 CN13IE CN12IE CN11IE CN10IE — ...
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... NOTES: DS70143B-page 68 Preliminary © 2005 Microchip Technology Inc. ...
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... These Operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit Timer1 module. © 2005 Microchip Technology Inc. 16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle match value preloaded into the Period register PR1, then resets to ‘ ...
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... Period register and be reset to 0x0000. When a match between the timer and the Period regis- ter occurs, an interrupt can be generated if the respective timer interrupt enable bit is asserted. Preliminary TSYNC Sync 1 0 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 © 2005 Microchip Technology Inc. ...
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... XTAL SOSCO pF 100K © 2005 Microchip Technology Inc. 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the Period register and is then reset to ‘0’. ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit Note: Refer to dsPIC30F Family Reference Manual (DS70046) for ...
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... Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 interrupt enable bit (T3IE). © 2005 Microchip Technology Inc. 16-bit Timer Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers. Each timer can be set up in either 16-bit Timer mode or 16-bit Synchronous Counter mode. See Section 9.0 “ ...
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... Timer configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70143B-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 Q D TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control Preliminary Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2005 Microchip Technology Inc. ...
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... Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2005 Microchip Technology Inc. PR2 Comparator x 16 TMR2 TGATE TON 1 x Gate Sync PR3 Comparator x 16 TMR3 ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). Preliminary © 2005 Microchip Technology Inc. ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70143B-page 78 Preliminary © 2005 Microchip Technology Inc. ...
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... T4CK Note: Timer configuration bit T32 (T4CON<3>) must be set to ‘ bits are respective to the T4CON register. © 2005 Microchip Technology Inc. • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral modules, such as input capture and ...
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... Timer5: TCS = 1 (16-bit counter) TCS = 0, TGATE = 1 (gated time accumulation) DS70143B-page 80 PR4 Comparator x 16 TMR4 Q TGATE TON 1 x Gate Sync PR5 Comparator x 16 TMR5 TGATE Sync Preliminary Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2005 Microchip Technology Inc. ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... NOTES: DS70143B-page 82 Preliminary © 2005 Microchip Technology Inc. ...
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... Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2005 Microchip Technology Inc. These Operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC DSC devices contain capture channels (i ...
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... IFSx status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC control register. Preliminary © 2005 Microchip Technology Inc. module is defined as ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... NOTES: DS70143B-page 86 Preliminary © 2005 Microchip Technology Inc. ...
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... TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2005 Microchip Technology Inc. The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Fault condition has occurred. This state will be main- tained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits. Preliminary . © 2005 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2005 Microchip Technology Inc. When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS ...
Page 93
... Both the transmit buffer (SPIxTXB) and the receive buffer (SPIxRXB) are mapped to the same register address, SPIxBUF. © 2005 Microchip Technology Inc. In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPIxBUF. The interrupt is generated at the middle of the transfer of the last bit ...
Page 94
... Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Preliminary Secondary Primary F Prescaler CY Prescaler 1:1 – 1 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2005 Microchip Technology Inc. ...
Page 95
... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2005 Microchip Technology Inc. 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
Page 96
TABLE 14-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 TABLE 14-2: SPI2 REGISTER MAP SFR ...
Page 97
... Thus, the I C module can operate either as a slave master bus. FIGURE 15-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2005 Microchip Technology Inc. 15.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
Page 98
... I2CRSR LSB Addr_Match I2CADD Start and Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Preliminary Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2005 Microchip Technology Inc. ...
Page 99
... If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL. After 8 bits are © 2005 Microchip Technology Inc. received, if I2CRCV is not full or I2COV is not set, I2CRSR is transferred to I2CRCV. ACK is sent on the ninth clock ...
Page 100
... C module generates two interrupt flags, MI2CIF Master Interrupt Flag) and SI2CIF (I rupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. Preliminary © 2005 Microchip Technology Inc. 2 CRCV 2 C Slave Inter- ...
Page 101
... Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2005 Microchip Technology Inc. 2 15. Master Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition ...
Page 102
... C OPERATION DURING CPU IDLE MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. Preliminary © 2005 Microchip Technology Inc. ...
Page 103
TABLE 15-1: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN — ...
Page 104
... NOTES: DS70143B-page 102 Preliminary © 2005 Microchip Technology Inc. ...
Page 105
... Internal Data Bus UTXBRK Data UxTX Parity Note © 2005 Microchip Technology Inc. 16.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 106
... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Preliminary Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF © 2005 Microchip Technology Inc. ...
Page 107
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2005 Microchip Technology Inc. 16.3 Transmitting Data 16.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 108
... The receive buffer is full. b) The Receive Shift register is full, but unable to transfer the character to the receive buffer. c) The Stop bit of the character in the UxRSR is detected, indicating that the UxRSR needs to transfer the character to the buffer. Preliminary © 2005 Microchip Technology Inc. RXB) X ...
Page 109
... FERR bit set. The break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2005 Microchip Technology Inc. 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this spe- cial mode in which a 9th bit (URX8) value of ‘ ...
Page 110
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. Preliminary © 2005 Microchip Technology Inc. ...
Page 111
TABLE 16-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG 0212 ...
Page 112
... NOTES: DS70143B-page 110 Preliminary © 2005 Microchip Technology Inc. ...
Page 113
... CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2005 Microchip Technology Inc. The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 114
... Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit Err Pas Bus Off Error Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX © 2005 Microchip Technology Inc. ...
Page 115
... Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2005 Microchip Technology Inc. The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 116
... End of Frame (EOF) field. Reading the RXnIF flag will indicate which receive buffer caused the interrupt. • Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. Preliminary © 2005 Microchip Technology Inc. ...
Page 117
... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2005 Microchip Technology Inc. Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 118
... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 sec corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point Preliminary . Also, by definition, Q Sync © 2005 Microchip Technology Inc. ...
Page 119
... SEG2PH<2:0> (CiCFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg © 2005 Microchip Technology Inc. 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and interpreted as the value of that respec fixed tive bit ...
Page 120
TABLE 17-1: CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1RXF0SID 0300 — — — C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier <5:0> C1RXF1SID 0308 — — ...
Page 121
TABLE 17-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B1 0356 Transmit Buffer 1 Byte 1 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C ...
Page 122
TABLE 17-2: CAN2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2RXF0SID — — — 03C0 C2RXF0EIDH 03C2 — — — — C2RXF0EIDL 03C4 Receive Acceptance Filter 0 Extended Identifier <5:0> C2RXF1SID — — — ...
Page 123
TABLE 17-2: CAN2 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2TX1B1 0416 Transmit Buffer 1 Byte 1 C2TX1B2 0418 Transmit Buffer 1 Byte 3 C2TX1B3 041A Transmit Buffer 1 Byte 5 C2TX1B4 041C ...
Page 124
... NOTES: DS70143B-page 122 Preliminary © 2005 Microchip Technology Inc. ...
Page 125
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. © 2005 Microchip Technology Inc. 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled. ...
Page 126
... DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70143B-page 124 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer Control Unit 15 DCI Shift Register Preliminary SCKD CSCK FSD COFS 0 CSDI CSDO © 2005 Microchip Technology Inc. ...
Page 127
... Note: The COFSG control bits will have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. © 2005 Microchip Technology Inc. 18.3.4 FRAME SYNC MODE CONTROL BITS The type of frame sync signal is selected using the Frame Synchronization (COFSM< ...
Page 128
... LSB S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 MSB LSB MSB 2 S protocol does not specify word length – this Preliminary LSB © 2005 Microchip Technology Inc. ...
Page 129
... When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. © 2005 Microchip Technology Inc. EQUATION 18-2: The required bit clock frequency will be determined by the system sampling rate and frame size. Typical bit ...
Page 130
... In this case, the buffer control unit counter would be incre- mented twice during a data frame but only one receive register location would be filled with data. Preliminary © 2005 Microchip Technology Inc. ...
Page 131
... DCI module. © 2005 Microchip Technology Inc. 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. The TMPTY bit is set when the contents of the transmit buffer registers are transferred to the transmit shadow registers ...
Page 132
... The 20-bit AC-Link mode functions similar to the Multi- Channel mode of the DCI module, except for the duty cycle of the frame synchronization signal. The AC-Link frame synchronization signal should remain high for 16 CSCK cycles and should be low for the following 240 cycles. Preliminary © 2005 Microchip Technology Inc. ...
Page 133
... The user must also select the frame length and data word size using the COFSG and WS control bits in the DCICON2 SFR. © 2005 Microchip Technology Inc. 2 18.7 FRAME AND DATA WORD ...
Page 134
TABLE 18-2: DCI REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DCICON1 0240 DCIEN — DCISIDL — DCICON2 0242 — — — — DCICON3 0244 — — — — DCISTAT 0246 — — — — ...
Page 135
... AN14 1111 AN15 V AN1 © 2005 Microchip Technology Inc. The ADC module has six 16-bit registers: • ADC Control Register 1 (ADCON1) • ADC Control Register 2 (ADCON2) • ADC Control Register 3 (ADCON3) • ADC Input Select Register (ADCHS) • ADC Port Configuration Register (ADPCFG) • ...
Page 136
... The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. Preliminary © 2005 Microchip Technology Inc. ...
Page 137
... EQUATION 19-1: ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2005 Microchip Technology Inc. The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V Specifications section for minimum T operating conditions ...
Page 138
... REF REF circuit. DS70143B-page 136 R Max V Temperature DD s 2.5 k 4.5V to 5.5V -40°C to +85°C 2.5 k 3.0V to 5.5V -40°C to +125°C Preliminary Channels Configuration REF REF CH X ANx S/H ADC REF REF ANx S/H ADC ANx REF © 2005 Microchip Technology Inc. ...
Page 139
... The following figure depicts the recommended circuit for the conversion rates above 100 ksps. The dsPIC30F6014A is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC 0 The configuration procedures below give the required setup values for the conversion speeds above 100 ksps ...
Page 140
... The internal holding capacitor will discharged state prior to each sample operation. ) imped 250 IC Sampling Switch leakage V = 0.6V T 500 nA PIN Preliminary AD CONV AD . The combined impedance HOLD , is 2 After the HOLD = DAC capacitance = negligible © 2005 Microchip Technology Inc. ...
Page 141
... Integer 0 © 2005 Microchip Technology Inc. If the ADC interrupt is enabled, the device will wake-up from Sleep. If the ADC interrupt is not enabled, the ADC module will then be turned off, although the ADON bit will remain set ...
Page 142
... Any external components connected (via high-impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. Preliminary and V as ESD the input voltage exceeds this SS © 2005 Microchip Technology Inc. ...
Page 143
TABLE 19-2: ADC REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ...
Page 144
... NOTES: DS70143B-page 142 Preliminary © 2005 Microchip Technology Inc. ...
Page 145
... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2005 Microchip Technology Inc. 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 146
... LP oscillator can be conveniently shared as system clock, as well as Real-Time Clock for Timer1. 3: Any higher will violate PLL input range. 4: Any lower will violate PLL input range. 5: Requires external R and C. Frequency operation MHz. DS70143B-page 144 Description (1) (2) (3) (3) (1) (4) (4) (1)(4) (5) /4 output OSC (5) Preliminary © 2005 Microchip Technology Inc. (1) ...
Page 147
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2005 Microchip Technology Inc. F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer ...
Page 148
... OSC2 Function OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKOUT 1 1 CLKOUT OSC2 0 0 (Note (Note (Note © 2005 Microchip Technology Inc. ...
Page 149
... The state of this signal is reflected in the read-only LOCK bit in the OSCCON register. © 2005 Microchip Technology Inc. 20.2.5 FAST RC OSCILLATOR (FRC) The FRC oscillator is a fast (7.37 MHz ±2% nominal) internal RC oscillator ...
Page 150
... Note: The application should not attempt to switch to a clock of frequency lower than 100 kHz when the Fail-Safe Clock Monitor is enabled. If clock switching is performed, the device may generate an oscillator fail trap and switch to the fast RC oscillator. Preliminary © 2005 Microchip Technology Inc. ...
Page 151
... Loaded with NOSC<2:0> at the completion of a successful clock switch. Set to FRC value when FSCM detects a failure and switches clock to FRC. bit 11 Unimplemented: Read as ‘0’ © 2005 Microchip Technology Inc. 20.3 Oscillator Control Registers The oscillators are controlled with two SFRs, OSCCON and OSCTUN and one Configuration register, FOSC ...
Page 152
... Request Oscillator switch to selection specified by NOSCG<2:0> bits 0 = Oscillator switch is complete Legend Readable bit -n = Value at POR y = Value set from Configuration bits on POR DS70143B-page 150 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary x = Bit is unknown © 2005 Microchip Technology Inc. ...
Page 153
... Center Frequency, Oscillator is running at calibrated frequency 1111 = 1110 = 1101 = 1100 = 1011 = 1010 = 1001 = 1000 = Minimum Frequency Legend Readable bit -n = Value at POR y = Value set from Configuration bits on POR © 2005 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — Writable bit U = Unimplemented bit, read as ‘ ...
Page 154
... Legend Readable bit DS70143B-page 152 — — — R/P — — — U R/P R/P — Writable bit U = Unimplemented bit, read as ‘0’ Preliminary U U — — bit 16 R/P R/P FOS<2:0> bit 8 R/P R/P R/P FPR<4:0> bit 0 © 2005 Microchip Technology Inc. ...
Page 155
... Reset BOREN Trap Conflict Illegal Opcode/ Uninitialized W Register © 2005 Microchip Technology Inc. Different registers are affected in different ways by various Reset conditions. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register are set or cleared differently in different Reset situations, as indicated in Table 20-5 ...
Page 156
... The timing for the SYSRST signal is shown in Figure 20-3 through Figure 20-5. T OST T PWRT T OST T PWRT Preliminary , which is POR s and ensures that the device bias ) is applied. The T parameter PWRT + T . When these delays POR PWRT ) DD ): CASE 1 DD © 2005 Microchip Technology Inc. ...
Page 157
... If the FSCM is disabled and the system clock has not started, the device will frozen state at the Reset vector until the system clock starts. From the user’s perspective, the device will appear Reset until a system clock is available. © 2005 Microchip Technology Inc. T OST T PWRT 20 ...
Page 158
... Overstress (EOS). Note: Dedicated supervisory devices, such as the MCP1XX and MCP8XX, may also be used as an external Power-on Reset circuit. Preliminary EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW V POWER-UP MCLR dsPIC30F C power-up slope DD powers DD pin breakdown due to Elec- PP © 2005 Microchip Technology Inc. ...
Page 159
... Clock Failure Trap 0x000004 Trap Reset 0x000000 Illegal Operation Reset 0x000000 Legend unchanged Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. © 2005 Microchip Technology Inc. TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ...
Page 160
... In order to have the small- est possible start-up delay when waking up from Sleep, one of these faster wake-up options should be selected before entering Sleep. Preliminary , T and T delays are POR LOCK PWRT (~ applied. This is the smallest . PWRT delay and OST POR © 2005 Microchip Technology Inc. ...
Page 161
... CPU and instruction execution begins immedi- ately, starting with the instruction following the PWRSAV instruction. © 2005 Microchip Technology Inc. Any interrupt that is individually enabled (using IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR ...
Page 162
... If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/ EMUC3 is selected as the debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions ( are not multiplexed with the PGD and PGC pin functions. Preliminary © 2005 Microchip Technology Inc PGC, PGD and the SS ...
Page 163
TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F601XA SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name . RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 — COSC<2:0> — OSCTUN 0744 — — — — — ...
Page 164
... NOTES: DS70143B-page 162 Preliminary © 2005 Microchip Technology Inc. ...
Page 165
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2005 Microchip Technology Inc. Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 166
... Programmer’s Reference Manual. Description {W13, [W13 {0...15} {0x0000...0x1FFF} {0,1} {0...15} {0...31} {0...255} {0...255} for Byte mode, {0:1023} for Word mode {0...16384} {0...65535} {0...8388608}; LSB must be 0 {-512...511} {-32768...32767} {-16...16} Preliminary © 2005 Microchip Technology Inc. ...
Page 167
... Y data space prefetch address register for DSP instructions {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions © 2005 Microchip Technology Inc. Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0..W15} {W0 ...
Page 168
... Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Preliminary © 2005 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV,Z ...
Page 169
... DEC Ws,Wd 28 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd © 2005 Microchip Technology Inc. Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 170
... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd + 1):W(nd) Prefetch and store accumulator Preliminary © 2005 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 None ...
Page 171
... Ws,Wd 67 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd © 2005 Microchip Technology Inc. Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * ...
Page 172
... Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary © 2005 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 None 1 1 None ...
Page 173
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2005 Microchip Technology Inc. 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 174
... MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. Preliminary © 2005 Microchip Technology Inc. ...
Page 175
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2005 Microchip Technology Inc. 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 176
... Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest Product Selector Guide (DS00148) for the complete list of demonstration, development and evaluation kits. Preliminary © 2005 Microchip Technology Inc. ® L security ICs, CAN ® ...
Page 177
... V Range Temp Range DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2005 Microchip Technology Inc. (1) (except V and MCLR) ................................................ -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ...................................................................................................± ...............................................................................................................200 mA pin, inducing currents greater than 80 mA, may cause latchup. ...
Page 178
... INT Typ Max Unit Notes 34 °C °C °C °C/W 1 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0- © 2005 Microchip Technology Inc. ...
Page 179
... All I/O pins are configured as inputs and pulled to V MCLR = V , WDT, FSCM and BOR are disabled. CPU, SRAM, program memory and data memory are DD operational. No peripheral modules are operating. © 2005 Microchip Technology Inc Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 180
... OSC1 DD Preliminary +85°C for Industrial +125°C for Extended 8 MIPS 10 MIPS 16 MIPS 20 MIPS . DD © 2005 Microchip Technology Inc. ...
Page 181
... All I/O pins are configured as inputs and pulled to V MCLR = V , WDT, FSCM and BOR are disabled. CPU, SRAM, program memory and data memory are DD operational. No peripheral modules are operating. © 2005 Microchip Technology Inc. ) (CONTINUED) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 182
... Preliminary +85°C for Industrial +125°C for Extended 0.128 MIPS LPRC (512 kHz) 1 MIPS 1.8 MIPS FRC (7.37 MHz) 4 MIPS © 2005 Microchip Technology Inc. ...
Page 183
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with core off, clock on and all modules turned off. IDLE © 2005 Microchip Technology Inc. ) (CONTINUED) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 184
... A 85°C A 125°C A -40°C A 25° 85°C A 125°C Preliminary ) PD +85°C for Industrial +125°C for Extended (3) Base Power-Down Current (3) Watchdog Timer Current: I WDT (3) Timer1 w/32 kHz Crystal BOR (3) BOR On: I © 2005 Microchip Technology Inc. ...
Page 185
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2005 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 186
... Preliminary +85°C for Industrial A T +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode C™ mode © 2005 Microchip Technology Inc. ...
Page 187
... These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) RESET (due to BOR) © 2005 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min (2) transition LVDL = 0000 — ...
Page 188
... Industrial A +125°C for Extended A Conditions - +85° Using EECON to read/write V = Minimum operating MIN voltage ms Provided no other specifications are violated mA Row Erase - +85° Minimum operating MIN voltage Provided no other specifications are violated ms mA Row Erase mA Bulk Erase © 2005 Microchip Technology Inc. ...
Page 189
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Pin FIGURE 23-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT © 2005 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T Operating voltage V range as described in DC Spec Section 23 ...
Page 190
... HS/3 with 4x PLL 25 MHz HS/3 with 8x PLL (3) 22.5 MHz HS/3 with 16x PLL — kHz LP — — See parameter OS10 for F value OSC DC ns See Table 23-16 — — ns See parameter D031 — ns See parameter D032 ). CY © 2005 Microchip Technology Inc. ...
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... AC CHARACTERISTICS Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. © 2005 Microchip Technology Inc. = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° (1) ...
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... Extended Conditions T +85° 3.0-3. +125° 4.5-5. +85° 3.0-3. +125° 4.5-5. +85° 3.0-3. +125° 4.5-5. +125° 4.5-5. +125° 3.0-5. +85° 3.0-3. +125° 3.0-3. +85° 4.5-5. +125° 4.5-5. © 2005 Microchip Technology Inc. ...
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... Measurements are taken in RC mode and EC mode where CLKOUT output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2005 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ...
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... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. DS70143B-page 192 SY10 SY20 SY13 Preliminary © 2005 Microchip Technology Inc. SY13 ...
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... Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2005 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min ...
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... Industrial A +125°C for Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz 1.5 T — CY © 2005 Microchip Technology Inc. ...
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... TtxP TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer3 and Timer5 are Type C. © 2005 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C Min Typ Synchronous, ...
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... Industrial +125°C for Extended Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) T +85°C for Industrial A T +125°C for Extended A Units Conditions ns See Parameter D032 ns See Parameter D031 © 2005 Microchip Technology Inc. ...
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... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2005 Microchip Technology Inc. OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
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... CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. DS70143B-page 198 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 Preliminary CS20 CS21 70 LSb HIGH-Z CS31 LSb IN © 2005 Microchip Technology Inc. ...