DSPIC30F6014A-30I/PF Microchip Technology Inc., DSPIC30F6014A-30I/PF Datasheet - Page 50

• Manufacturer Part Number: DSPIC30F6014A-30I/PF
• Description: 16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6014A-30I/PF

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN/I2C/SPI/UART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

dsPIC30F6011A/6012A/6013A/6014A
5.
6.
Stack Error Trap:
This trap is initiated under the following conditions:
1.
2.
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
5.3.2
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-1 is implemented,
which may require the user to check if other traps are
pending in order to completely correct the fault.
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be Acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, Acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs so that the condition may be
detected in software.
DS70143B-page 48
Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
The Stack Pointer is loaded with a value which
is greater than the (user programmable) limit
value written into the SPLIM register (stack
overflow).
The Stack Pointer is loaded with a value which
is less than 0x0800 (simple stack underflow).
HARD AND SOFT TRAPS
Preliminary
FIGURE 5-1:
5.4
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
Interrupt Request (IRQ) is indicated by the flag bit
being equal to a ‘1’ in an IFSx register. The IRQ will
cause an interrupt to occur if the corresponding bit in
the Interrupt Enable (IECx) register is set. For the
remainder of the instruction cycle, the priorities of all
pending interrupt requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current Program
Counter and the low byte of the processor STATUS
register (SRL), as shown in Figure 5-2. The low byte of
the STATUS register contains the processor priority
level at the time prior to the beginning of the interrupt
cycle. The processor then loads the priority level for
this interrupt into the STATUS register. This action will
disable all lower priority interrupts until the completion
of the Interrupt Service Routine.
AIVT
Interrupt Sequence
IVT
Oscillator Fail Trap Vector
Address Error Trap Vector
Oscillator Fail Trap Vector
Address Error Trap Vector
Reset - GOTO Instruction
Stack Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Math Error Trap Vector
Reset - GOTO Address
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
TRAP VECTORS
© 2005 Microchip Technology Inc.
Reserved
Reserved
Reserved
Reserved
~
~
~
~
~
~
0x000000
0x000002
0x000004
0x000014
0x00007E
0x000080
0x000082
0x000084
0x000094
0x0000FE