DSPIC30F6014A-30I/PF Microchip Technology Inc., DSPIC30F6014A-30I/PF Datasheet - Page 231

• Manufacturer Part Number: DSPIC30F6014A-30I/PF
• Description: 16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6014A-30I/PF

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN/I2C/SPI/UART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

F
Fast Context Saving............................................................ 49
Flash Program Memory ...................................................... 51
I
I/O Pin Specifications
I/O Ports .............................................................................. 63
I
I
I
I
I
I
Idle Current (I
In-Circuit Debugger (ICD 2) .............................................. 160
In-Circuit Serial Programming (ICSP) ......................... 51, 143
Initialization Condition for RCON Register Case 1 ........... 157
Initialization Condition for RCON Register Case 2 ........... 157
Input Capture (CAPX) Timing Characteristics .................. 196
Input Capture Module ......................................................... 83
Input Capture Operation During Sleep and Idle Modes ...... 84
© 2005 Microchip Technology Inc.
2
2
2
2
2
2
C 10-bit Slave Mode Operation ........................................ 97
C 7-bit Slave Mode Operation .......................................... 97
C Master Mode Operation ................................................ 99
C Master Mode Support ................................................... 99
C Module .......................................................................... 95
S Mode Operation .......................................................... 131
Control Registers ........................................................ 52
Input .......................................................................... 183
Output ....................................................................... 184
Parallel (PIO) .............................................................. 63
Reception.................................................................... 98
Transmission............................................................... 97
Reception.................................................................... 97
Transmission............................................................... 97
Baud Rate Generator................................................ 100
Clock Arbitration........................................................ 100
Multi-Master Communication, Bus Collision
Reception.................................................................... 99
Transmission............................................................... 99
Addresses ................................................................... 97
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................... 99
Interrupts..................................................................... 98
IPMI Support ............................................................... 99
Operating Function Description .................................. 95
Operation During CPU Sleep and Idle Modes .......... 100
Pin Configuration ........................................................ 95
Programmer’s Model................................................... 95
Register Map............................................................. 101
Registers..................................................................... 95
Slope Control .............................................................. 99
Software Controlled Clock Stretching (STREN = 1).... 98
Various Modes ............................................................ 95
Data Justification....................................................... 131
Frame and Data Word Length Selection................... 131
Interrupts..................................................................... 84
Register Map............................................................... 85
NVMADR ............................................................ 52
NVMADRU.......................................................... 52
NVMCON ............................................................ 52
NVMKEY............................................................. 52
and Bus Arbitration ........................................... 100
Master Mode ..................................................... 206
Slave Mode ....................................................... 208
Master Mode ..................................................... 207
Slave Mode ....................................................... 209
Master Mode ..................................................... 206
Slave Mode ....................................................... 208
IDLE
) ............................................................ 180
dsPIC30F6011A/6012A/6013A/6014A
Input Capture Timing Requirements................................. 196
Input Change Notification Module....................................... 67
Instruction Addressing Modes ............................................ 39
Instruction Set
Internet Address ............................................................... 233
Interrupt Controller
Interrupt Priority .................................................................. 46
Interrupt Sequence ............................................................. 48
Interrupts ............................................................................ 45
L
Load Conditions................................................................ 187
Low Voltage Detect (LVD) ................................................ 158
Low-Voltage Detect Characteristics.................................. 184
LVDL Characteristics ........................................................ 185
M
Memory Organization 1, 9, 15, 25, 39, 45, 51, 57, 63, 69, 73,
Microchip Internet Web Site.............................................. 233
Modes of Operation
Module ................................................................................ 95
Modulo Addressing ............................................................. 40
MPLAB ASM30 Assembler, Linker, Librarian ................... 172
MPLAB ICD 2 In-Circuit Debugger ................................... 173
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development Environment
MPLAB PM3 Device Programmer .................................... 173
MPLINK Object Linker/MPLIB Object Librarian ................ 172
CPU Idle Mode ........................................................... 84
CPU Sleep Mode........................................................ 84
Register Map for dsPIC30F6011A/6012 A
Register Map for dsPIC30F6011A/6012A
Register Map for dsPIC30F6013A/6014A
Register Map for dsPIC30F6013A/6014A
(Bits 7-0) ..................................................................... 67
File Register Instructions ............................................ 39
Fundamental Modes Supported ................................. 39
MAC Instructions ........................................................ 40
MCU Instructions ........................................................ 39
Move and Accumulator Instructions ........................... 40
Other Instructions ....................................................... 40
Overview................................................................... 166
Summary .................................................................. 163
Register Map .............................................................. 50
Interrupt Stack Frame................................................. 49
79, 83, 87, 91, 95, 103, 111, 123, 133, 163
Core Register Map ..................................................... 36
Disable...................................................................... 113
Initialization............................................................... 113
Listen All Messages.................................................. 113
Listen Only................................................................ 113
Loopback .................................................................. 113
Normal Operation ..................................................... 113
Applicability................................................................. 42
Operation Example..................................................... 41
Start and End Address ............................................... 41
W Address Register Selection.................................... 41
In-Circuit Emulator.................................................... 173
In-Circuit Emulator.................................................... 173
oftware...................................................................... 171
(Bits 7-0) ............................................................. 67
(Bits 15-8) ........................................................... 67
(Bits 15-8) ........................................................... 67
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