DSPIC30F6014A-30I/PF Microchip Technology Inc., DSPIC30F6014A-30I/PF Datasheet - Page 234

• Manufacturer Part Number: DSPIC30F6014A-30I/PF
• Description: 16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6014A-30I/PF

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN/I2C/SPI/UART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

dsPIC30F6011A/6012A/6013A/6014A
Trap Vectors........................................................................ 48
Traps ................................................................................... 47
U
UART Module
UART Operation
Unit ID Locations............................................................... 143
Universal Asynchronous Receiver Transmitter. See UART
W
Wake-up from Sleep ......................................................... 143
Wake-up from Sleep and Idle.............................................. 49
Watchdog Timer (WDT) ............................................ 143, 158
WWW Address.................................................................. 233
WWW, On-Line Support........................................................ 8
DS70143B-page 232
Hard and Soft .............................................................. 48
Sources ....................................................................... 47
Address Detect Mode ............................................... 107
Auto Baud Support.................................................... 108
Baud Rate Generator ................................................ 107
Enabling and Setting Up ........................................... 105
Framing Error (FERR)............................................... 107
Idle Status ................................................................. 107
Loopback Mode ........................................................ 107
Operation During CPU Sleep and Idle Modes .......... 108
Overview ................................................................... 103
Parity Error (PERR) .................................................. 107
Receive Break........................................................... 107
Receive Buffer (UxRXB) ........................................... 106
Receive Buffer Overrun Error (OERR Bit) ................ 106
Receive Interrupt....................................................... 106
Receiving Data.......................................................... 106
Receiving in 8-bit or 9-bit Data Mode........................ 106
Reception Error Handling.......................................... 106
Transmit Break.......................................................... 106
Transmit Buffer (UxTXB)........................................... 105
Transmit Interrupt...................................................... 106
Transmitting Data...................................................... 105
Transmitting in 8-bit Data Mode ................................ 105
Transmitting in 9-bit Data Mode ................................ 105
UART1 Register Map ................................................ 109
UART2 Register Map ................................................ 109
Idle Mode .................................................................. 108
Sleep Mode ............................................................... 108
Enabling and Disabling ............................................. 158
Operation .................................................................. 158
Timing Characteristics .............................................. 192
Timing Requirements ................................................ 193
Address Error Trap ............................................. 47
Math Error Trap................................................... 47
Oscillator Fail Trap.............................................. 48
Stack Error Trap.................................................. 48
© 2005 Microchip Technology Inc.