DSPIC30F6014A-30I/PF Microchip Technology Inc., DSPIC30F6014A-30I/PF Datasheet - Page 59

• Manufacturer Part Number: DSPIC30F6014A-30I/PF
• Description: 16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6014A-30I/PF

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN/I2C/SPI/UART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

7.0
The Data EEPROM Memory is readable and writable
during normal operation over the entire V
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory, as well. As described in Section 6.5 “Control
Registers”, these registers are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR in conjunction with the
NVMADRU register are used to address the EEPROM
location being accessed. TBLRDL and TBLWTL
instructions are used to read and write data EEPROM.
The dsPIC30F devices have up to 8 Kbytes (4K
words) of data EEPROM with an address range from
0x7FF000 to 0x7FFFFE.
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write typ-
ically requires 2 ms to complete but the write time will
vary with voltage and temperature.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
© 2005 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F
Programmer’s Reference Manual (DS70030).
DATA EEPROM MEMORY
dsPIC30F6011A/6012A/6013A/6014A
DD
range. The
Preliminary
Control bit WR initiates write operations similar to pro-
gram Flash writes. This bit cannot be cleared, only set,
in software. They are cleared in hardware at the com-
pletion of the write operation. The inability to clear the
WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal opera-
tion. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.
7.1
A TBLRD instruction reads a word at the current pro-
gram word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4 as shown in Example 7-1.
EXAMPLE 7-1:
MOV
MOV
MOV
TBLRDL [ W0 ], W4
Note:
Reading the Data EEPROM
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
Interrupt flag bit NVMIF in the IFS0 regis-
ter is set when write is complete. It must be
cleared in software.
,
TBLPAG
DATA EEPROM READ
; Init Pointer
; read data EEPROM
DS70143B-page 57