DSPIC30F6014A-30I/PF Microchip Technology Inc., DSPIC30F6014A-30I/PF Datasheet - Page 230

• Manufacturer Part Number: DSPIC30F6014A-30I/PF
• Description: 16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6014A-30I/PF

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN/I2C/SPI/UART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

dsPIC30F6011A/6012A/6013A/6014A
D
Data Accumulators and Adder/Subtractor........................... 21
Data Address Space ........................................................... 31
Data Converter Interface (DCI) Module ............................ 123
Data EEPROM Memory ...................................................... 57
DC Characteristics ............................................................ 175
DCI Module
DS70143B-page 228
Data Space Write Saturation ...................................... 23
Overflow and Saturation ............................................. 21
Round Logic ................................................................ 22
Write Back................................................................... 22
Alignment .................................................................... 34
Alignment (Figure) ...................................................... 35
Effect of Invalid Memory Accesses (Table)................. 34
MCU and DSP (MAC Class) Instructions Example..... 34
Memory Map ............................................................... 31
Memory Map for dsPIC30F6011A/6013A ................... 32
Memory Map for dsPIC30F6012A/6014A ................... 33
Near Data Space ........................................................ 35
Software Stack ............................................................ 35
Spaces ........................................................................ 31
Width ........................................................................... 34
Erasing ........................................................................ 58
Erasing, Block ............................................................. 58
Erasing, Word ............................................................. 58
Protection Against Spurious Write .............................. 61
Reading....................................................................... 57
Write Verify ................................................................. 61
Writing ......................................................................... 59
Writing, Block .............................................................. 60
Writing, Word .............................................................. 59
Brown-out Reset ............................................... 185, 186
I/O Pin Input Specifications ....................................... 183
I/O Pin Output Specifications .................................... 184
Idle Current (I
Low-Voltage Detect................................................... 184
LVDL ......................................................................... 185
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 186
Bit Clock Generator................................................... 127
Buffer Alignment with Data Frames .......................... 129
Buffer Control ............................................................ 123
Buffer Data Alignment ............................................... 123
Buffer Length Control ................................................ 129
COFS Pin .................................................................. 123
CSCK Pin .................................................................. 123
CSDI Pin ................................................................... 123
CSDO Mode Bit ........................................................ 130
CSDO Pin ................................................................. 123
Data Justification Control Bit ..................................... 128
Device Frequencies for Common Codec
Digital Loopback Mode ............................................. 130
Enable ....................................................................... 125
Frame Sync Generator ............................................. 125
Frame Sync Mode Control Bits ................................. 125
I/O Pins ..................................................................... 123
Interrupts ................................................................... 130
Introduction ............................................................... 123
Master Frame Sync Operation .................................. 125
Operation .................................................................. 125
Operation During CPU Idle Mode ............................. 130
Operation During CPU Sleep Mode .......................... 130
Receive Slot Enable Bits........................................... 128
CSCK Frequencies (Table)............................... 127
IDLE
) .................................................... 180
DD
)............................................. 177
PD
) ........................................ 182
Development Support ....................................................... 171
Device Configuration
Device Configuration Registers ........................................ 159
Device Overview1, 9, 15, 25, 39, 45, 51, 57, 63, 69, 73, 79, 83,
Disabling the UART .......................................................... 105
Divide Support .................................................................... 18
DSP Engine ........................................................................ 19
Dual Output Compare Match Mode .................................... 88
E
Electrical Characteristics .................................................. 175
Enabling and Setting Up UART
Enabling the UART ........................................................... 105
Equations
Errata .................................................................................... 8
External Clock Timing Characteristics
External Clock Timing Requirements ............................... 188
External Interrupt Requests ................................................ 49
Receive Status Bits................................................... 129
Register Map ............................................................ 132
Sample Clock Edge Control Bit ................................ 128
Slave Frame Sync Operation.................................... 126
Slot Enable Bits Operation with Frame Sync............ 128
Slot Status Bits ......................................................... 130
Synchronous Data Transfers .................................... 128
Timing Characteristics
Timing Requirements
Transmit Slot Enable Bits ......................................... 128
Transmit Status Bits.................................................. 129
Transmit/Receive Shift Register ............................... 123
Underflow Mode Control Bit...................................... 130
Word Size Selection Bits .......................................... 125
Register Map ............................................................ 161
FBORPOR ................................................................ 159
FGS .......................................................................... 159
FOSC........................................................................ 159
FWDT ....................................................................... 159
87, 91, 95, 103, 111, 123, 133, 163
Instructions (Table) ..................................................... 18
Multiplier ..................................................................... 21
Continuous Pulse Mode.............................................. 88
Single Pulse Mode...................................................... 88
AC............................................................................. 187
DC ............................................................................ 175
Setting Up Data, Parity and Stop Bit Selections ....... 105
ADC Conversion Clock ............................................. 135
Baud Rate................................................................. 107
Bit Clock Frequency.................................................. 127
COFSG Period.......................................................... 125
Serial Clock Rate ...................................................... 100
Time Quantum for Clock Generation ........................ 117
Type A, B and C Timer ............................................. 194
Type A Timer ............................................................ 194
Type B Timer ............................................................ 195
Type C Timer ............................................................ 195
AC-Link Mode................................................... 200
Multichannel, I
AC-Link Mode................................................... 200
Multichannel, I
2
2
S Modes................................... 198
S Modes................................... 199
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