PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 120

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F785/HV785
15.3.1
External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin
is edge-triggered; either rising, if INTEDG bit
(OPTION_REG<6>) is set, or falling, if INTEDG bit is
clear. When a valid edge appears on the RA2/AN2/
T0CKI/INT/C1OUT pin, the INTF bit (INTCON<1>) is
set. This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the Interrupt Service Routine before re-
enabling this interrupt. The RA2/AN2/T0CKI/INT/
C1OUT interrupt can wake-up the processor from
Sleep if the INTE bit was set prior to going into Sleep.
The status of the GIE bit decides whether or not the
processor branches to the interrupt vector following
wake-up (0004h). See Section 15.6 “Power-Down
Mode (Sleep)” for details on Sleep and Figure 15-10
for timing of wake-up from Sleep through RA2/AN2/
T0CKI/INT/C1OUT interrupt.
FIGURE 15-7:
DS41249D-page 118
Note:
RA2/AN2/T0CKI/INT/C1OUT
INTERRUPT
The ANSEL0 (91h), and ANSEL1 (93h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
IOC-RA0
IOC-RA1
IOC-RA2
IOC-RA3
IOC-RA4
IOC-RA5
TMR2IF
TMR2IE
TMR1IE
TMR1IF
CCP1IF
CCP1IE
IOCA0
IOCA1
IOCA2
IOCA3
IOCA4
IOCA5
OSFIF
OSFIE
ADIF
ADIE
EEIE
C1IF
C1IE
C2IF
C2IE
EEIF
INTERRUPT LOGIC
Note 1:
Preliminary
RAIE
INTF
INTE
RAIF
PEIE
T0IF
T0IE
GIE
Some peripherals depend upon the system clock for
operation. Since the system clock is suspended during Sleep, only
those peripherals which do not depend upon the system clock will wake
the part from Sleep. See Section 15.6.1 “Wake-up from Sleep”.
15.3.2
An overflow (FFh
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled
(INTCON<5>) bit. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
15.3.3
An input change on PORTA change sets the RAIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RAIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA register.
Note:
TMR0 INTERRUPT
PORTA INTERRUPT
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF inter-
rupt flag may not get set.
Wake-up (If in Sleep mode)
00h) in the TMR0 register will set
by
© 2006 Microchip Technology Inc.
setting/clearing
Interrupt to CPU
(1)
T0IE