PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 53

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

6.0
The Timer1 module is the 16-bit counter of the
PIC16F785/HV785. Figure 6-1 shows the basic block
diagram of the Timer1 module. Timer1 has the follow-
ing features:
• 16-bit timer/counter (TMR1H:TMR1L)
• Readable and writable
• Internal or external clock selection
• Synchronous or asynchronous operation
• Interrupt on overflow from FFFFh to 0000h
• Wake-up upon overflow (Asynchronous mode)
• Optional external enable input:
• Optional LP oscillator
FIGURE 6-1:
© 2006 Microchip Technology Inc.
- Selectable gate source; T1G or C2 output
- Selectable gate polarity (T1GINV)
Without CLKOUT
(T1GSS)
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G/OSC2/CLKOUT
Note 1: Timer1 increments on the rising edge.
INTOSC
TIMER1 MODULE WITH GATE
CONTROL
LP
Sleep
*
2: SYNCC2OUT is the synchronized output from Comparator 2 (See Figure 9-2 on 66).
ST Buffer is low power type when using LP OSC, or high-speed type when using T1CKI.
Set flag bit
TMR1IF on
Overflow
T1OSCEN
TIMER1 ON THE PIC16F785/HV785 BLOCK DIAGRAM
TMR1H
Oscillator
TMR1
(1)
TMR1L
Preliminary
*
Internal
Clock
F
OSC
Q
EN
D
/4
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to enable/disable Timer1 and
select the various features of the Timer1 module.
TMR1CS
Note:
1
0
To C2 Comparator Module
TMR1 Clock
PIC16F785/HV785
T1CKPS<1:0>
Additional information on timer modules is
available in the “PICmicro
MCU
(DS33023).
T1SYNC
SYNCC2OUT
Prescaler
1, 2, 4, 8
0
1
2
Family
TMR1ON
TMR1GE
TMR1ON
TMR1GE
(2)
Synchronized
clock input
T1GSS
Sleep input
Synchronize
Reference
1
0
det
DS41249D-page 51
®
Mid-Range
T1GINV
Manual”