PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 38

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F785/HV785
REGISTER 4-2:
4.2
Every PORTA pin on the PIC16F785/HV785 has an
interrupt-on-change option and a weak pull-up option.
The next three sections describe these functions.
REGISTER 4-3:
DS41249D-page 36
Additional Pin Functions
bit 7-6
bit 5-0
bit 7-6
bit 5-0
TRISA: PORTA TRI-STATE REGISTER (ADDRESS: 85h, 185h)
WPUA: WEAK PULL-UP REGISTER (ADDRESS: 95h)
bit 7
bit 7
Unimplemented: Read as ‘0’
TRISA<5:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Unimplemented: Read as ‘0’
WPUA<5:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Legend:
R = Readable bit
-n = Value at POR
Legend:
R = Readable bit
-n = Value at POR
Note 1: TRISA<3> always reads ‘1’.
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
U-0
U-0
—
—
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
3: The RA3 pull-up is automatically enabled when configured as MCLR in the
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
(TRISA = 0).
Configuration Word.
U-0
U-0
—
—
TRISA5
WPUA5
R/W-1
R/W-1
Preliminary
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
(2)
(4)
TRISA4
WPUA4
R/W-1
R/W-1
4.2.1
Each of the PORTA pins has an individually config-
urable internal weak pull-up. Control bits WPUAx
enable or disable each pull-up. Refer to Register 4-3.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the RAPU bit
(OPTION_REG<7>). The weak pull-up on RA3 is auto-
matically enabled when RA3 is configured as MCLR.
(1), (2)
(2)
(4)
WPUA3
TRISA3
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-1
WEAK PULL-UPS
(1)
(3)
TRISA2
WPUA2
R/W-1
R/W-1
(1), (2)
© 2006 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
TRISA1
WPUA1
R/W-1
R/W-1
WPUA0
TRISA0
R/W-1
R/W-1
bit 0
bit 0