PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 63

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.3.2
The PWM duty cycle is specified by writing to the
CCPR1L
(CCP1CON<5:4>) bits. Up to 10 bits of resolution is
available. The CCPR1L contains the eight MSbs and
the DC1B<1:0> contains the two LSbs. CCPR1L and
DC1B<1:0> can be written to at any time. In PWM
mode, CCPR1H is a read-only register. This 10-bit
value is represented by CCPR1L (CCP1CON<5:4>).
Equation 8-2 is used to calculate the PWM duty cycle
in time.
EQUATION 8-2:
TABLE 8-3:
© 2006 Microchip Technology Inc.
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
PWM duty cycle
Note 1: Changing duty cycle will cause a glitch.
PWM Frequency
PWM DUTY CYCLE
register
=
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F
T
CCPR1L:CCP1CON<5:4>
OSC
PWM DUTY CYCLE
and
(TMR2 prescale value)
to
1.22 kHz
0xFF
the
16
10
(1)
DC1B<1:0>
4.88 kHz
0xFF
Preliminary
10
4
(1)
19.53 kHz
CCPR1L and DC1B<1:0> can be written to at any time,
but the duty cycle value is not latched into CCPR1H
until after a match between PR2 and TMR2 occurs
(i.e. the period is complete). In PWM mode, CCPR1H
is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Because of the buffering, the module waits until the
timer resets, instead of starting immediately. This
means that enhanced PWM waveforms do not exactly
match the standard PWM waveforms, but are instead
offset by one full instruction cycle (4 T
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the RC5/CCP1 pin is cleared.
The maximum PWM resolution is a function of PR2 as
shown by Equation 8-3.
EQUATION 8-3:
0xFF
Note:
10
1
PIC16F785/HV785
Resolution
If the PWM duty cycle value is longer than
the PWM period, the assigned PWM pin(s)
will remain unchanged.
78.12 kHz
0x3F
1
8
OSC
=
PWM RESOLUTION
log
----------------------------------------- - bits
= 20 MHz)
4 PR2
log
156.3 kHz
0x1F
2
1
7
+
DS41249D-page 61
1
OSC
).
208.3 kHz
0x17
6.6
1