PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 56

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F785/HV785
6.5
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software
(Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
6.5.1
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples in the “PICmicro
Reference Manual” (DS33023) show how to read and
write Timer1 when it is running in Asynchronous mode.
TABLE 6-1:
DS41249D-page 54
0Bh,
8Bh
0Ch
0Eh
0Fh
10h
11Bh
8Ch
91h
Legend:
Addr
Note:
INTCON
PIR1
TMR1L
TMR1H
T1CON
CM2CON1 MC1OUT MC2OUT
PIE1
ANSEL0
Timer1 Operation in
Asynchronous Counter Mode
Name
are
The ANSEL0 (91h) register must be initial-
ized to configure an analog channel as a
digital input. Pins configured as analog
inputs will read ‘0’.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
needed
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
REGISTERS ASSOCIATED WITH TIMER1
T1GINV
ANS7
Bit 7
EEIF
EEIE
GIE
to
TMR1GE
®
ANS6
PEIE
ADIF
ADIE
Bit 6
Mid-Range MCU Family
read/write
T1CKPS1
CCP1IF
CCP1IE
ANS5
Bit 5
T0IE
—
the
T1CKPS0
ANS4
INTE
Bit 4
C2IF
C2IE
timer
—
Preliminary
T1OSCEN
ANS3
RAIE
C1IE
Bit 3
C1IF
—
6.6
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated for 32.768 kHz. It will
continue to run during Sleep. It is primarily intended for
a 32.768 kHz tuning fork crystal.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is also the LP oscillator or is
derived from the internal oscillator. As with the system
LP oscillator, the user must provide a software time
delay to ensure proper oscillator start-up.
Sleep mode will not disable the system clock when the
system clock and Timer1 share the LP oscillator.
TRISA<5> and TRISA<4> bits are set when the Timer1
oscillator is enabled. RA5 and RA4 read as ‘0’ and
TRISA<5> and TRISA<4> bits read as ‘1’.
6.7
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device will wake-up and jump
to the Interrupt Service Routine (0004h) on an overflow.
If the GIE bit is clear, execution will continue with the
next instruction.
Note:
T1SYNC
OSFIF
OSFIE
ANS2
Bit 2
T0IF
—
Timer1 Oscillator
Timer1 Operation During Sleep
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
TMR1CS
TMR2IF
TMR2IE
T1GSS
ANS1
INTF
Bit 1
TMR1ON
C2SYNC
TMR1IF
TMR1IE
ANS0
© 2006 Microchip Technology Inc.
Bit 0
RAIF
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
00-- --10
0000 0000
1111 1111
POR, BOR
Value on:
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
00-- --10
0000 0000
1111 1111
Value on
all other
Resets