PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 71

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.2
The comparator outputs are read through the
CM1CON0, COM2CON0 or CM2CON1 registers.
CM1CON0 and CM2CON0 each contain the individual
comparator output of Comparator 1 and Comparator 2,
respectively. CM2CON2 contains a mirror copy of both
comparator outputs facilitating a simultaneous read of
both comparators. These bits are read-only. The
comparator outputs may also be directly output to the
RA2/AN2/T0CKI/INT/C1OUT and RC4/C2OUT/PH2
I/O pins. When enabled, multiplexers in the output path
of the RA2 and RC4 pins will switch and the output of
each pin will be the unsynchronized output of the com-
parator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 9-1 and Figure 9-2
show the output block diagrams for Comparators 1 and
2, respectively.
The TRIS bits will still function as an output enable/
disable for the RA2/AN2/T0CKI/INT/C1OUT and RC4/
C2OUT/PH2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C1POL and C2POL bits (CMxCON0<4>).
Timer1 gate source can be configured to use the T1G
pin or Comparator 2 output as selected by the T1GSS
bit (CM2CON1<1>). The Timer1 gate feature can be
used to time the duration or interval of analog events.
The output of Comparator 2 can also be synchronized
with
(CM2CON1<0>). When enabled, the output of
Comparator 2 is latched on the falling edge of the
Timer1 clock source. If a prescaler is used with Timer1,
Comparator 2 is latched after the prescaler. To prevent
a race condition, the Comparator 2 output is latched on
the falling edge of the Timer1 clock source and Timer1
increments on the rising edge of its clock source. See
the Comparator 2 Block Diagram (Figure 9-2) and the
Timer1
information.
It is recommended to synchronize Comparator 2 with
Timer1 by setting the C2SYNC bit when Comparator 2
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if Comparator 2 changes
during an increment.
© 2006 Microchip Technology Inc.
Timer1
Comparator Outputs
Block
by
Diagram
setting
(Figure 6-1)
the
C2SYNC
for
more
Preliminary
bit
9.3
The comparator interrupt flags are set whenever there
is a change in the output value of its respective compar-
ator. Software will need to maintain information about
the status of the output bits, as read from
CM2CON0<7:6>, to determine the actual change that
has occurred. The CxIF bits, PIR1<4:3>, are the
Comparator Interrupt Flags. Each comparator interrupt
bit must be reset in software by clearing it to ‘0’. Since
it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
The CxIE bits (PIE1<4:3>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupts. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CxIF bits will still be set if an interrupt condition occurs.
The comparator interrupt of the PIC16F785/HV785
differs from previous designs in that the interrupt flag is
set by the mismatch edge and not the mismatch level.
This means that the interrupt flag can be reset without
the additional step of reading or writing the CMxCON0
register to clear the mismatch registers. When the
mismatch registers are not cleared, an interrupt will not
occur when the comparator output returns to the
previous state. When the mismatch registers are
cleared, an interrupt will occur when the comparator
returns to the previous state.
9.4
A Reset forces all registers to their Reset state. This
disables both comparators.
Note 1: If a change in the CMxCON0 register
PIC16F785/HV785
2: When either comparator is first enabled,
Effects of Reset
Comparator Interrupts
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF (PIR1<4:3>)
interrupt flag may not get set.
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is sta-
ble. Allow about 1 s for bias settling then
clear the mismatch condition and inter-
rupt flags before enabling comparator
interrupts.
DS41249D-page 69