PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 13

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 2-2:
© 2006 Microchip Technology Inc.
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note
Addr
1:
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
WDTCON
ADRESH
ADCON0
Name
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(1)
PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1
Holding Register for the Most Significant Byte of the 16-bit TMR1
Timer2 Module Register
Capture/Compare/PWM Register1 Low Byte
Capture/Compare/PWM Register1 High Byte
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Most Significant 8 bits of the left justified A/D result or 2 bits of right justified result
T1GINV
ADFM
Bit 7
EEIF
RC7
RB7
IRP
GIE
—
—
—
—
—
TOUTPS3
TMR1GE
VCFG
Bit 6
PEIE
ADIF
RC6
RP1
RB6
—
—
—
—
TOUTPS2
T1CKPS1
CCP1IF
DC1B1
CHS3
Bit 5
T0IE
RP0
RA5
RB5
RC5
—
—
Write Buffer for Upper 5 bits of Program Counter
TOUTPS1
T1CKPS0
WDTPS3
DC1B0
Preliminary
CHS2
Bit 4
INTE
C2IF
RA4
RC4
RB4
TO
T1OSCEN
TOUTPS0
WDTPS2
CCP1M3
CHS1
RAIE
Bit 3
C1IF
RA3
RC3
PD
—
TMR2ON
CCP1M2
WDTPS1
T1SYNC
OSFIF
CHS0
PIC16F785/HV785
Bit 2
RA2
RC2
T0IF
—
Z
GO/DONE
T2CKPS1
TMR1CS
WDTPS0
CCP1M1
TMR2IF
INTF
Bit 1
RA1
RC1
DC
—
T2CKPS0
TMR1ON
SWDTEN
CCP1M0
TMR1IF
ADON
Bit 0
RAIF
RC0
RA0
—
C
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--x0 x000
xx00 ----
00xx 0000
---0 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
---0 1000 122,114
xxxx xxxx
0000 0000
POR, BOR
Value on:
DS41249D-page 11
—
—
—
—
—
—
—
—
—
—
22,114
49,114
21,114
15,114
22,114
35,114
42,114
45,114
21,114
17,114
19,114
52,114
52,114
53,114
55,114
55,114
58,114
58,114
58,114
81,114
83,114
Page
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