PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 141
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PIC16F726-I/SP
Manufacturer Part Number
PIC16F726-I/SP
Description
28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F726-ISP.pdf
(266 pages)
Specifications of PIC16F726-I/SP
A/d Inputs
11-Channel, 8-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Frequency
20 MHz
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
I2C, SPI, AUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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15.3
The PWM mode generates a Pulse-Width Modulated
signal on the CCPx pin. The duty cycle, period and
resolution are determined by the following registers:
• PR2
• T2CON
• CCPRxL
• CCPxCON
In Pulse-Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the CCPx pin.
Figure 15-3 shows a simplified block diagram of PWM
operation.
Figure 15-4 shows a typical waveform of the PWM
signal.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, refer to Section 15.3.8
“Setup for PWM Operation”.
FIGURE 15-3:
© 2008 Microchip Technology Inc.
Note 1:
CCPRxH
Duty Cycle Registers
Comparator
2:
CCPRxL
PWM Mode
PR2
TMR2
Comparator
The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (F
2 bits of the prescaler, to create the 10-bit time
base.
In PWM mode, CCPRxH is a read-only register.
(2)
(Slave)
(1)
SIMPLIFIED PWM BLOCK
DIAGRAM
Clear Timer2,
toggle CCPx pin and
latch duty cycle
CCPxCON<5:4>
S
R
Q
TRIS
OSC
CCPx
), or
Preliminary
PIC16F72X/PIC16LF72X
The PWM output (Figure 15-4) has a time base
(period) and a time that the output stays high (duty
cycle).
FIGURE 15-4:
15.3.1
In PWM mode, the CCPx pin is multiplexed with the
PORT data latch. The user must configure the CCPx
pin as an output by clearing the associated TRIS bit.
Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.
Note:
Pulse Width
TMR2 = 0
CCPX PIN CONFIGURATION
Clearing the CCPxCON register will
relinquish CCPx control of the CCPx pin.
Period
CCP PWM OUTPUT
TMR2 = CCPRxL:CCPxCON<5:4>
TMR2 = PR2
DS41341B-page 139
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