PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 95
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PIC16F726-I/SP
Manufacturer Part Number
PIC16F726-I/SP
Description
28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F726-ISP.pdf
(266 pages)
Specifications of PIC16F726-I/SP
A/d Inputs
11-Channel, 8-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Frequency
20 MHz
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
I2C, SPI, AUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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8.0
Device Configuration consists of Configuration Word 1
and Configuration Word 2 registers, Code Protection
and Device ID.
REGISTER 8-1:
© 2008 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
Note 1:
U-1
—
—
2:
3:
4:
(4)
DEVICE CONFIGURATION
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire program memory will be erased when the code protection is turned off.
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
MPLAB
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger
PLLEN: INTOSC PLL Enable bit
0 = INTOSC Frequency is 500 kHz
1 = INTOSC Frequency is 16 MHz (32x)
Unimplemented: Read as ‘1’
BORV: Brown-out Reset Voltage selection bit
0 = Brown-out Reset Voltage (V
1 = Brown-out Reset Voltage (V
BOREN<1:0>: Brown-out Reset Selection bits
0x = BOR disabled (Preconditioned State)
10 = BOR enabled during operation and disabled in Sleep
11 = BOR enabled
Unimplemented: Read as ‘1’
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: RE3/MCLR pin function select bit
1 = RE3/MCLR pin function is MCLR
0 = RE3/MCLR pin function is digital input, MCLR internally tied to V
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
®
IDE masks unimplemented Configuration bits to ‘0’.
R/P-1
CP
—
CONFIG1: CONFIGURATION WORD REGISTER 1
P = Programmable bit
W = Writable bit
‘1’ = Bit is set
DEBUG
MCLRE
R/P-1
R/P-1
(2)
BOR
BOR
PWRTE
) set to 2.5 V nominal
) set to 1.9 V nominal
PLLEN
R/P-1
R/P-1
Preliminary
(3)
PIC16F72X/PIC16LF72X
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WDTE
8.1
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1
register at 2007h and Configuration Word 2 register at
2008h. These registers are only accessible during
programming.
U-1
R/P-1
—
(4)
Configuration Words
DD
FOSC2
BORV
R/P-1
R/P-1
x = Bit is unknown
BOREN1
FOSC1
R/P-1
R/P-1
DS41341B-page 93
BOREN0
FOSC0
R/P-1
R/P-1
bit 8
bit 0
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