PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 24
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PIC16F726-I/SP
Manufacturer Part Number
PIC16F726-I/SP
Description
28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F726-ISP.pdf
(266 pages)
Specifications of PIC16F726-I/SP
A/d Inputs
11-Channel, 8-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Frequency
20 MHz
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
I2C, SPI, AUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F72X/PIC16LF72X
TABLE 2-1:
DS41341B-page 22
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note
Address
Bank 0
(2)
(2)
(2)
(2)
(3)
(1, 2)
(2)
1:
2:
3:
4:
5:
6:
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
Accessible only when SSPM<3:0> = 1001.
Accessible only when SSPM<3:0> ≠ 1001.
This bit is always ‘1’ as RE3 is input only.
Name
PIC16F72X/PIC16LF72X SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module Register
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register (LSB)
Capture/Compare/PWM Register (MSB)
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
A/D Result Register
TMR1CS1 TMR1CS0 T1CKPS1
TMR1GIF
WCOL
SPEN
Bit 7
RA7
RB7
RC7
RD7
GIE
IRP
—
—
—
—
—
—
—
TOUTPS3 TOUTPS2 TOUTPS1
SSPOV
PEIE
ADIF
Bit 6
RP1
RA6
RB6
RC6
RD6
RX9
—
—
—
—
—
—
SSPEN
DC1B1
DC2B1
SREN
CHS3
RCIF
Bit 5
RC5
RD5
T0IE
RP0
RA5
RB5
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
Preliminary
T1CKPS0
DC1B0
DC2B0
CREN
CHS2
Bit 4
INTE
RC4
RD4
TXIF
CKP
RA4
RB4
TO
—
—
T1OSCEN
TOUTPS0
CCP1M3
CCP2M3
ADDEN
SSPM3
SSPIF
CHS1
RBIE
Bit 3
RC3
RD3
RA3
RB3
RE3
PD
—
TMR2ON
T1SYNC
CCP1M2
CCP2M2
CCP1IF
SSPM2
RE2
FERR
CHS0
Bit 2
T0IF
RA2
RB2
RC2
RD2
—
Z
(3)
GO/DONE
T2CKPS1 T2CKPS0 -000 0000
CCP1M1
CCP2M1
TMR2IF
SSPM1
RE1
OERR
Bit 1
INTF
RA1
RB1
RC1
RD1
DC
—
—
(3)
© 2008 Microchip Technology Inc.
TMR1ON
CCP1M0
CCP2M0
TMR1IF
CCP2IF
SSPM0
RE0
ADON
RX9D
Bit 0
RBIF
RA0
RB0
RC0
RD0
C
(3)
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
---0 0000
0000 000x
0000 0000
---- ---0
xxxx xxxx
xxxx xxxx
0000 00-0
0000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 000x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
--00 0000
POR, BOR
Value on:
109,38
118,38
118,38
122,38
125,38
126,38
167,38
184,38
135,38
135,38
134,38
153,38
152,38
150,38
135,38
135,38
134,38
103,39
102,39
29,38
28,38
25,38
29,38
52,38
61,38
71,38
78,38
83,38
28,38
44,38
47,38
48,38
Page
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