PAC-POWR1220AT8-HS-EVN Lattice, PAC-POWR1220AT8-HS-EVN Datasheet - Page 2

• Manufacturer Part Number: PAC-POWR1220AT8-HS-EVN
• Description: Supervisory Circuits Pwr Mgr Hercules Std Development Kit
• Manufacturer: Lattice
• Series: ispPAC®, MachXO, Herculesr

Specifications of PAC-POWR1220AT8-HS-EVN

• Silicon Manufacturer: Lattice Semiconductor
• Kit Application Type: Power Management
• Application Sub Type: Power Manager
• Kit Contents: Preloaded Board, Eval Board, AC Adapter, USB Connector Cable
• Rohs Compliant: Yes
• Main Purpose: Power Management, ORing Controller / Hot Swap Controller
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR1220AT8, LCMXO2280
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
(HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs can
provide up to 12V for driving the gates of n-channel MOSFETs so that they can be used as high-side power
switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down.
The ispPAC-POWR1220AT8 incorporates a 48-macrocell CPLD that can be used to implement complex state
machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status
of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as
inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable
timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using Logi-
Builder™, an easy-to-learn language integrated into the PAC-Designer
monitor the status of any of the analog input channel comparators or the digital inputs.
In addition to the sequence control functions, the ispPAC-POWR1220AT8 incorporates eight DACs for generating
trimming voltage to control the output voltage of a DC-DC converter. The trimming voltage can be set to four hard-
ware selectable preset values (voltage profiles) or can be dynamically loaded in to the DAC through the I
Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various
load conditions using the Digital Closed Loop Control mode. The operating voltage profile can either be selected
using external hardware pins or through the PLD outputs.
The on-chip 10-bit A/D converter can both be used to monitor the V
implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the
monitoring and trimming section of the ispPAC-POWR1220AT8 device.
The I
inputs, read back the status of each of the V
trol the output pins, and load the DACs for the generation of the trimming voltage of the external DC-DC converter.
Figure 1-1. ispPAC-POWR1220AT8 Block Diagram
2
C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V
VMON10GS
VMON11GS
VMON12GS
VMON1GS
VMON2GS
VMON3GS
VMON4GS
VMON5GS
VMON6GS
VMON7GS
VMON8GS
VMON9GS
VMON10+
VMON11+
VMON12+
VMON1+
VMON2+
VMON3+
VMON4+
VMON5+
VMON6+
VMON7+
VMON8+
VMON9+
VPS0
VPS1
IN1
IN2
IN3
IN4
IN5
IN6
ADC
JTAG LOGIC
MON
comparator and PLD outputs, control logic signals IN2 to IN5, con-
OSCILLATOR
CONTROL LOGIC
48 MACROCELLS
CLOCK
MARGIN/TRIM
83 INPUTS
CPLD
1-2
TIMERS
(4)
MON
ispPAC-POWR1220AT8 Data Sheet
®
software. Control sequences are written to
voltage through the I
INTERFACE
VOLTAGE OUTPUT
I
2
C
DACS (8)
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
2
C bus as well as for
TRIM1
TRIM2
TRIM3
TRIM4
TRIM5
TRIM6
TRIM7
TRIM8
HVOUT1
HVOUT2
HVOUT3
HVOUT4
OUT5/SMBA
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
2
C bus.
MON