PAC-POWR1220AT8-HS-EVN Lattice, PAC-POWR1220AT8-HS-EVN Datasheet - Page 21

• Manufacturer Part Number: PAC-POWR1220AT8-HS-EVN
• Description: Supervisory Circuits Pwr Mgr Hercules Std Development Kit
• Manufacturer: Lattice
• Series: ispPAC®, MachXO, Herculesr

Specifications of PAC-POWR1220AT8-HS-EVN

• Silicon Manufacturer: Lattice Semiconductor
• Kit Application Type: Power Management
• Application Sub Type: Power Manager
• Kit Contents: Preloaded Board, Eval Board, AC Adapter, USB Connector Cable
• Rohs Compliant: Yes
• Main Purpose: Power Management, ORing Controller / Hot Swap Controller
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR1220AT8, LCMXO2280
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
PLD Block
Figure 1-10 shows the ispPAC-POWR1220AT8 PLD architecture, which is derived from the Lattice's ispMACH™
4000 CPLD. The PLD architecture allows the flexibility in designing various state machines and control functions
used for power supply management. The AND array has 83 inputs and generates 243 product terms. These 243
product terms are divided into three groups of 81 for each of the generic logic blocks, GLB1, GLB2, and GLB3.
Each GLB is made up of 16 macrocells. In total, there are 48 macrocells in the ispPAC-POWR1220AT8 device. The
output signals of the ispPAC-POWR1220AT8 device are derived from GLBs as shown in Figure 1-10. Additionally,
the GLB3 generates the timer control and trimming block controls.
Figure 1-10. ispPAC-POWR1220AT8 PLD Architecture
Macrocell Architecture
The macrocell shown in Figure 1-11 is the heart of the PLD. The basic macrocell has five product terms that feed
the OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to
function as a D-Type or T-Type flip-flop. Combinatorial functions are realized by bypassing the flip-flop. The polarity
control and XOR gates provide additional flexibility for logic synthesis. The flip-flop’s clock is driven from the com-
mon PLD clock that is generated by dividing the 8 MHz master clock (MCLK) by 32. The macrocell also supports
asynchronous reset and preset functions, derived from either product terms, the global reset input, or the power-on
reset signal. The resources within the macrocells share routing and contain a product term allocation array. The
product term allocation array greatly expands the PLD’s ability to implement complex logical functions by allowing
logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions.
All the digital inputs are registered by MCLK and the VMON comparator outputs are registered by the PLD Clock to
synchronize them to the PLD logic.
Global Reset
(Resetb pin)
AGOOD
IN[1:6]
VMON[1-12]
24
6
4
Timer0
Timer1
Timer2
Timer3
Register
Register
MCLK
Input
Input
Timer Clock
Feedback
Output
48
IRP
AND Array
83 Inputs
243 PT
14
81
81
81
PLD Clock
1-21
Generic Logic Block
Generic Logic Block
Generic Logic Block
16 Macrocell
16 Macrocell
16 Macrocell
GLB1
81 PT
GLB2
81 PT
GLB3
81 PT
ispPAC-POWR1220AT8 Data Sheet
HVOUT[1..4],
OUT[5..8]
PLD_CLT_EN,
PLD_VPS[0:1]
OUT[9..16]
OUT[17..20]