PAC-POWR1220AT8-HS-EVN Lattice, PAC-POWR1220AT8-HS-EVN Datasheet - Page 45

• Manufacturer Part Number: PAC-POWR1220AT8-HS-EVN
• Description: Supervisory Circuits Pwr Mgr Hercules Std Development Kit
• Manufacturer: Lattice
• Series: ispPAC®, MachXO, Herculesr

Specifications of PAC-POWR1220AT8-HS-EVN

• Silicon Manufacturer: Lattice Semiconductor
• Kit Application Type: Power Management
• Application Sub Type: Power Manager
• Kit Contents: Preloaded Board, Eval Board, AC Adapter, USB Connector Cable
• Rohs Compliant: Yes
• Main Purpose: Power Management, ORing Controller / Hot Swap Controller
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR1220AT8, LCMXO2280
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
data in, and then executing a program configuration instruction, after which the data is transferred to internal
E
instructions are defined that access all data registers and perform other internal control operations. For compatibil-
ity between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func-
tionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by
the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 1-37 shows how
the instruction and various data registers are organized in an ispPAC-POWR1220AT8.
Figure 1-37. ispPAC-POWR1220AT8 TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine
whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists
of a small 16-state controller design. In a given state, the controller responds according to the level on the TMS
input as shown in Figure 1-38. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data
Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-
Reset, Run- Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-
Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This
allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the
power-on default state.
2
CMOS cells. It is these non-volatile cells that store the configuration or the ispPAC-POWR1220AT8. A set of
TDI
TEST ACCESS PORT (TAP)
CFG ADDRESS REGISTER (12 BITS)
INSTRUCTION REGISTER (8 BITS)
ADDRESS REGISTER (169 BITS)
CFG DATA REGISTER (156 BITS)
TCK
IDCODE REGISTER (32 BITS)
DATA REGISTER (243 BITS)
BYPASS REGISTER (1 BIT)
UES REGISTER (32 BITS)
LOGIC
TMS
1-45
OUTPUT
LATCH
TDO
ispPAC-POWR1220AT8 Data Sheet
NON-VOLATILE
MEMORY
E
2
CMOS