PAC-POWR1220AT8-HS-EVN Lattice, PAC-POWR1220AT8-HS-EVN Datasheet - Page 29

• Manufacturer Part Number: PAC-POWR1220AT8-HS-EVN
• Description: Supervisory Circuits Pwr Mgr Hercules Std Development Kit
• Manufacturer: Lattice
• Series: ispPAC®, MachXO, Herculesr

Specifications of PAC-POWR1220AT8-HS-EVN

• Silicon Manufacturer: Lattice Semiconductor
• Kit Application Type: Power Management
• Application Sub Type: Power Manager
• Kit Contents: Preloaded Board, Eval Board, AC Adapter, USB Connector Cable
• Rohs Compliant: Yes
• Main Purpose: Power Management, ORing Controller / Hot Swap Controller
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR1220AT8, LCMXO2280
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
DAC Register I
microcontroller to control the DC-DC converter output voltage. The microcontroller updates the contents of the
DAC Register I
ter and is reset to 80H (DAC at Bipolar zero) upon power-on. The external microcontroller writes the correct DAC
code in this DAC Register I
Digital Closed Loop Trim Mode
Closed loop trim mode operation can be used when tight control over the DC-DC converter output voltage at a
desired value is required. The closed loop trim mechanism operates by comparing the measured output voltage of
the DC-DC converter with the internally stored voltage setpoint. The difference between the setpoint and the actual
DC-DC converter voltage generates an error voltage. This error voltage adjusts the DC-DC converter output volt-
age toward the setpoint. This operation iterates until the setpoint and the DC-DC converter voltage are equal.
Figure 1-19 shows the closed loop trim operation of a TrimCell. At regular intervals (as determined by the Update
Rate Control register) the ispPAC-POWR1220AT8 device initiates the closed loop power supply voltage correction
cycle through the following blocks:
Figure 1-19. Digital Closed Loop Trim Operation
The closed loop trim cycle interval is programmable and is set by the update rate control register. The following
table lists the programmable update interval that can be selected by the update rate register.
POWR1220AT8
• Non-volatile Setpoint register stores the desired output voltage
• On-chip ADC is used to measure the voltage of the DC-DC converter
• Three-state comparator is used to compare the measured voltage from the ADC with the Setpoint regis-
• Channel polarity control determines the polarity of the error signal
• Closed loop trim register is used to compute and store the DAC code corresponding to the error voltage.
• The DAC in the TrimCell is used to generate the analog error voltage that adjusts the attached DC-DC con-
ter contents. The output of the three state comparator can be one of the following:
The contents of the Closed Loop Trim will be incremented or decremented depending on the channel polar-
ity and the three-state comparator output. If the three-state comparator output is 0, the closed loop trim reg-
ister contents are left unchanged.
verter output voltage.
Three-State
COMPARE
• +1 if the setpoint voltage is greater than the DC-DC converter voltage
• -1 if the setpoint voltage is less than the DC-DC converter voltage
• 0 if the setpoint voltage is equal to the DC-DC converter voltage
DIGITAL
(+1/0/-1)
2
SETPOINT
(E
C on the fly to set the trimming voltage to a desired value. The DAC Register I
2
C Select Mode: This mode is used if the power management arrangement requires an external
2
CMOS)
PLD_CLT_EN
CONTROL
2
UPDATE
C before enabling the programmable power supply.
RATE
POLARITY
CHANNEL
(E
2
+/-1
CMOS)
E
DAC Register I
2
DAC Register 3
DAC Register 2
DAC Register 1
DAC Register 0
CMOS Registers
Trim Register
Closed Loop
2
C
1-29
Control (E
Profile 0 Mode
2
Profile Control
TRIM CELL
CMOS)
(Pins/ PLD)
ADC
DAC
ispPAC-POWR1220AT8 Data Sheet
VMONx
TRIMx
2
C is a volatile regis-
TRIMIN
VOUT
GND
CONVERTER
DC-DC