PAC-POWR1220AT8-HS-EVN Lattice, PAC-POWR1220AT8-HS-EVN Datasheet - Page 25

• Manufacturer Part Number: PAC-POWR1220AT8-HS-EVN
• Description: Supervisory Circuits Pwr Mgr Hercules Std Development Kit
• Manufacturer: Lattice
• Series: ispPAC®, MachXO, Herculesr

Specifications of PAC-POWR1220AT8-HS-EVN

• Silicon Manufacturer: Lattice Semiconductor
• Kit Application Type: Power Management
• Application Sub Type: Power Manager
• Kit Contents: Preloaded Board, Eval Board, AC Adapter, USB Connector Cable
• Rohs Compliant: Yes
• Main Purpose: Power Management, ORing Controller / Hot Swap Controller
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR1220AT8, LCMXO2280
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
When the VPS[1:0] = 00, representing Voltage Profile 0: (Voltage Profile 0 is recommended to be used for the nor-
mal circuit operation)
The output voltage of the DC-DC converter controlled by the Trim 1 pin of the ispPAC-POWR1220AT8 will be 1V
and that TrimCell is operating in closed loop trim mode. At the same time, the DC-DC converters controlled by Trim
2, Trim 3 and Trim 8 pins output 1.2V, 1.5V and 3.3V respectively.
When the VPS[1:0] = 01, representing Voltage Profile 1 being active:
The DC-DC output voltage controlled by Trim 1, 2, 3, and 8 pins will be 1.05V, 1.26V, 1.57V, and 3.46V. These sup-
ply voltages correspond to 5% above their respective normal operating voltage (also called as margin high).
Similarly, when VPS[1:0] = 11, all DC-DC converters are margined low by 5%.
Figure 1-15. ispPAC-POWR1220AT8 Trim and Margin Block
There are eight TrimCells in the ispPAC-POWR1220AT8 device, enabling simultaneous control of up to eight indi-
vidual power supplies. Each TrimCell can generate up to four trimming voltages to control the output voltage of the
DC-DC converter.
VPS[0:1]
Read – 10-bit ADC Code
Input From ADC Mux
ispPAC-POWR1220AT8
Margin/Trim Block
(Closed Loop)
(I
(I
(Register 0)
TrimCell
TrimCell
TrimCell
TrimCell
2
2
C Update)
C Update)
PLD Control Signals
#1
#2
#3
#8
PLD_CLT_EN,
PLD_VPS[0:1]
Trim 1
Trim 2
Trim 3
Trim 8
1-25
R1*
R2*
R3*
R8*
*Indicates resistor network
V
V
V
V
IN
IN
IN
IN
Trim-in
Trim-in
Trim-in
Trim-in
DC-DC
DC-DC
DC-DC
DC-DC
ispPAC-POWR1220AT8 Data Sheet
1.2V (I
1.5V (I
3.3V (EE) 3.46V
1V (CLT) 1.05V
0
2
2
DC-DC Output Voltage
C) 1.26V
C) 1.57V
Controlled by Profiles
1
0.97V
1.16V
1.45V
3.20V
2
0.95V
1.14V
1.42V
3.13V
3