PAC-POWR1220AT8-HS-EVN Lattice, PAC-POWR1220AT8-HS-EVN Datasheet - Page 35

• Manufacturer Part Number: PAC-POWR1220AT8-HS-EVN
• Description: Supervisory Circuits Pwr Mgr Hercules Std Development Kit
• Manufacturer: Lattice
• Series: ispPAC®, MachXO, Herculesr

Specifications of PAC-POWR1220AT8-HS-EVN

• Silicon Manufacturer: Lattice Semiconductor
• Kit Application Type: Power Management
• Application Sub Type: Power Manager
• Kit Contents: Preloaded Board, Eval Board, AC Adapter, USB Connector Cable
• Rohs Compliant: Yes
• Main Purpose: Power Management, ORing Controller / Hot Swap Controller
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR1220AT8, LCMXO2280
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 1-10. ADC Input Attenuator Control
The input selector may be set to monitor any one of the twelve VMON inputs, the VCCA input, or the VCCINP
input. Table 1-11 shows the codes associated with each input selection.
Table 1-11. V
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conver-
sion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conver-
sion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by
performing two I
mended that the I
command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time
(see T
Note that if the I
conversion is to wait the minimum specified time (T
than that cannot be guaranteed. In other words, if the I
not assert even though a valid conversion result is available.
To insure every ADC conversion result is valid, preferred operation is to clock I
DONE bit status or wait for the full T
request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second
request is complete.
The status of the digital input lines may also be monitored and controlled through I
shows the I
INPUT_STATUS register, while input values to the PLD array may be set by writing to the INPUT_VALUE register.
To be able to set an input value for the PLD array, the input multiplexer associated with that bit needs to be set to
the I
2
C register setting in E
CONVERT
2
C interface to the IN[1:6] digital input lines. The input status may be monitored by reading the
MON
value in the specifications) and disregard checking the DONE bit.
2
C clock rate falls below 50kHz (see F
2
2
C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recom-
(ADC_MUX.3)
C master load a second conversion command only after the completion of the current conversion
Address Selection Table
SEL3
ATTEN (ADC_MUX.4)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
CMOS memory otherwise the PLD will receive its input from the INx pin.
0
1
(ADC_MUX.2)
CONVERT
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
Select Word
time period between subsequent ADC convert commands. If an I
(ADC_MUX.1)
CONVERT
Resolution
I 2 C
SEL1
1-35
2mV
6mV
2
C clock rate is less than 50kHz, the DONE bit may or may
0
0
1
1
0
0
1
1
0
0
1
1
0
0
note in specifications), the only way to insure a valid ADC
), as the operation of the DONE bit at clock rates lower
(ADC_MUX.0)
ispPAC-POWR1220AT8 Data Sheet
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Full-Scale Range
2.048 V
6.144 V
2
C at more than 50kHz and verify
Input Channel
VMON10
VMON11
VMON12
VCCINP
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
2
VCCA
C commands. Figure 1-26
2
C