ispPAC-POWR1220AT8-01T100I Lattice, ispPAC-POWR1220AT8-01T100I Datasheet - Page 27

• Manufacturer Part Number: ispPAC-POWR1220AT8-01T100I
• Description: Supervisory Circuits Prec Prg Pwr Spply S eq. Mon. Mrg Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1220AT8-01T100I

• Number Of Voltages Monitored: 12
• Undervoltage Threshold: 0.8 V
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 40 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 40mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 1-17. Voltage Profile Control
TrimCell Architecture
The TrimCell block diagram is shown in Figure 1-18. The 8-bit DAC at the output provides the trimming voltage
required to set the output voltage of a programmable supply. Each TrimCell can be operated in any one of the four
voltage profiles. In each voltage profile the output trimming voltage can be set to a preset value. There are six 8-bit
registers in each TrimCell that, depending on the operational mode, set the DAC value. Of these, four DAC values
(DAC Register 0 to DAC Register 3) are stored in the E
stored in volatile registers. Two multiplexers (Mode Mux and Profile Mux) control the routing of the code to the DAC.
The Profile Mux can be controlled by common TrimCell voltage profile control signals.
PLD Control Signals
VPS0
VPS1
PLD_VPS[0:1]
2
2
(E
INT/EXT
SELECT
2
CMOS)
1-27
2
2
CMOS memory while the remaining register contents are
ispPAC-POWR1220AT8
Margin/Trim Block
ispPAC-POWR1220AT8 Data Sheet
TrimCell
TrimCell
TrimCell
TrimCell
TrimCell
TrimCell
TrimCell
TrimCell
#1
#2
#3
#4
#5
#6
#7
#8
Trim 1
Trim 2
Trim 3
Trim 4
Trim 5
Trim 6
Trim 7
Trim 8