ispPAC-POWR1220AT8-01T100I Lattice, ispPAC-POWR1220AT8-01T100I Datasheet - Page 31

• Manufacturer Part Number: ispPAC-POWR1220AT8-01T100I
• Description: Supervisory Circuits Prec Prg Pwr Spply S eq. Mon. Mrg Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1220AT8-01T100I

• Number Of Voltages Monitored: 12
• Undervoltage Threshold: 0.8 V
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 40 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 40mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
RESETb Signal, RESET Command via JTAG or I
Activating the RESETb signal (Logic 0 applied to the RESETb pin) or issuing a reset instruction via JTAG or I
force the outputs to the following states independent of how these outputs have been configured in the PINS win-
dow:
At the conclusion of the RESET event, these outputs will go to the states defined by the PINS window, and if a
sequence has been programmed into the device, it will be re-started at the first step. The analog calibration will be
re-done and consequently, the VMONs, ADCs, and DACs will not be operational until 2.5 milliseconds (max.) after
the conclusion of the RESET event.
CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the ispPAC-
POWR1220AT8 device operation, results in the device aborting all operations and returning to the power-on reset
state. The status of the power supplies which are being enabled by the ispPAC-POWR1220AT8 will be determined
by the state of the outputs shown above.
I
I
devices on a circuit board. The ispPAC-POWR1220AT8 supports a 7-bit addressing of the I
tocol, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types
of modern power management systems. Figure 1-21 shows a typical I
PAC-POWR1220AT8s are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL
provides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I
the POWR1220AT8 is fully programmable through the JTAG port.
Figure 1-21. ispPAC-POWR1220AT8 in I
In both the I
ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The ispPAC-POWR1220AT8 is configured as a slave device, and cannot independently coordinate data transfers.
Each slave device on a given I
bit addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR1220AT8 device by
programming through JTAG. When selecting a device address, one should note that several addresses are
reserved by the I
assure bus compatibility. Table 1-8 lists these reserved addresses.
2
2
C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
C/SMBUS Interface
• OUT5-20 will go high-impedance.
• HVOUT pins programmed for open drain operation will go high-impedance.
• HVOUT pins programmed for FET driver mode operation will pull down.
SDA
V+
2
C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas-
MICROPROCESSOR
(I
2
2
SCL
C MASTER)
C and/or SMBus standards, and should not be assigned to ispPAC-POWR1220AT8 devices to
INTERRUPT
2
C bus is assigned a unique address. The ispPAC-POWR1220AT8 implements the 7-
SDA/SMDAT (DATA)
SCL/SMCLK (CLOCK)
SMBALERT
2
C/SMBUS System
SDA
POWR1220AT8
(I
1-31
2
C SLAVE)
SCL
2
C
OUT5/
SMBA
ispPAC-POWR1220AT8 Data Sheet
2
C configuration, in which one or more isp-
SDA
POWR1220AT8
(I
2
C SLAVE)
SCL
2
C communications pro-
OUT5/
SMBA
To Other
Devices
2
C address of
I
2
C
2
C will