PSB21384H-V13 Infineon Technologies, PSB21384H-V13 Datasheet - Page 181
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PSB21384H-V13
Manufacturer Part Number
PSB21384H-V13
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21384H-V13.pdf
(270 pages)
Specifications of PSB21384H-V13
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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6
The SCOUT can be reset completely by a hardware reset (pin RST). Additionally each
functional block can be reset separately via register SRES.
If enabled an exchange awake, subscriber awake or watchdog time-out can generate a
reset on pin RSTO/SDS2. A hardware reset always generates a reset on pin RSTO/
SDS2 (see figure 91).
Figure 91
Reset Generation. The above mentioned reset pulse widths are controlled by the
clock pin FSC
Data Sheet
Reset MODE1 Register
Internal Reset of all Registers
C/I Code Change
(Exchange Awake)
EAW
(Subscriber Awake)
Watchdog
Software Reset
(Register SRES)
Block
HDLC:
TR:
IOM:
MON:
CO:
CPLL:
Reset Functional Block
Reset
Register
(00
(30
(40
(5C
(60
H
H
H
H
H
-2F
-3B
-5B
-6F
-
-5F
H
H
H
H
H
)
)
)
)
)
t = 125 µs
125 µs < t < 250 µs
125 µs < t < 250 µs
SDSx_CR Register
SDSx
171
1
SDS2
SDS1 Pin
RST Pin
res_gen_s.vsd
PSB 21381/2
PSB 21383/4
2001-03-12
RSTO/
SDS2 Pin
Reset
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