PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 225
PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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7.3.9
Value after reset: 00
IOM_CR
SPU
0: The DU line is normally used for transmitting data
1: Setting this bit to ’1’ will pull the DU line to low. This will enforce connected layer 1
After a subsequent CIC-interrupt (C/I-code change; ISTA) and reception of the C/I-code
”PU” (Power Up indication in TE-mode) the microcontroller writes an AR or TIM
command as C/I-code in the CIX0-register, resets the SPU bit and wait for the following
CIC-interrupt.
TIC_DIS
0: The last octet of the last IOM time slot (TS 11) is used as TIC bus
1: The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used
EN_BCL
0: The BCL clock is disabled
1: The BCL clock is enabled
CLKM
If the transceiver is disabled (DIS_TR = ’1’) the DCL from the IOM-2 interface is an input.
With
0: A double clock per bit is expected
1: A single clock per bit is expected
DIS_OD
0: IOM outputs are open drain driver
1: IOM outputs are push pull driver
Data Sheet
devices to deliver IOM-clocking.
as every time slot.
IOM_CR - Control Register IOM Data
7
SPU
... Software Power UP
... TIC Bus Disable
... Enable Bit Clock BCL
... Clock Mode
... Open Drain
H
0
0
TIC_
DIS
215
EN_
BCL
CLKM DIS_
Detailed Register Description
OD
0
DIS_
IOM
PSB 21381/2
PSB 21383/4
RD/WR (56
2001-03-12
H
)
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