PSB21383HV1.3XT Infineon Technologies, PSB21383HV1.3XT Datasheet - Page 97
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PSB21383HV1.3XT
Manufacturer Part Number
PSB21383HV1.3XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383HV1.3XT.pdf
(270 pages)
Specifications of PSB21383HV1.3XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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2.3.7.2
Instead of using the integrated layer-1 statemachine it is also possible to implement the
layer-1 statemachine completely in software.
The internal layer-1 statemachine can be disabled by setting the L1SW bit in the
TR_CONF0 register to ’1’.
The transmitter is completely under control of the microcontroller via register TR_CMD ).
The status of the receiver is stored in register TR_STA and has to be evaluated by the
microcontroller. This register is updated continuously. If not masked a RIC interrupt is
generated by any change of the register contents. The interrupt is cleared after a read
access to this register.
Data Sheet
External Layer-1 Statemachine
87
PSB 21381/2
PSB 21383/4
Interfaces
2001-03-12
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