MT48LC16M16A2P-75 L Micron Technology Inc, MT48LC16M16A2P-75 L Datasheet - Page 36

• Manufacturer Part Number: MT48LC16M16A2P-75 L
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M16A2P-75 L

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

AUTO REFRESH
SELF REFRESH
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-
BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent,
so it must be issued each time a refresh is required. All active banks must be precharged
prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should
not be issued until the minimum
shown in Bank/Row Activation (page 50).
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. Regardless of device width,
the 256Mb SDRAM requires 8192 AUTO REFRESH cycles every 64ms (commercial and
industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command ev-
ery 7.813μs (commercial and industrial) or 1.953μs (automotive) will meet the refresh
requirement and ensure that each row is refreshed. Alternatively, 8192 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate (
(commercial and industrial) or 16ms (automotive).
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered-down. When in the self refresh mode, the SDRAM retains data
without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except
CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs
to the SDRAM become a “Don’t Care” with the exception of CKE, which must remain
LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking, caus-
ing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK
must be stable (stable clock is defined as a signal cycling within timing constraints speci-
fied for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two clocks) for
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
7.81μs or less, as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter.
Self refresh is not supported on automotive temperature (AT) devices.
36
t
RP has been met after the PRECHARGE command, as
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RAS and may remain in self refresh mode
256Mb: x4, x8, x16 SDRAM
© 1999 Micron Technology, Inc. All rights reserved.
t
RFC), once every 64ms
t
XSR because time is
Commands