MT48LC16M16A2P-75 L Micron Technology Inc, MT48LC16M16A2P-75 L Datasheet - Page 50

• Manufacturer Part Number: MT48LC16M16A2P-75 L
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M16A2P-75 L

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Bank/Row Activation
Figure 20: Example: Meeting
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a
row in that bank must be opened. This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated.
After a row is opened with the ACTIVE command, a READ or WRITE command can be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 20 (page 50), which cov-
ers any case where 2 <
other specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been precharged. The minimum time interval between
successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVE commands to different banks is defined
by
t
RRD.
CLK
t
RCD (MIN) When 2 <
ACTIVE
T0
t CK
t
RCD (MIN)/
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
NOP
t
RCD(MIN)
T1
50
t
RCD (MIN)/
t CK
t
RCD specification.
t
CK ≤ 3. (The same procedure is used to convert
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T2
t
CK < 3
t CK
READ or
WRITE
256Mb: x4, x8, x16 SDRAM
t
RCD (MIN) should be divided by
Don’t Care
T3
Bank/Row Activation
© 1999 Micron Technology, Inc. All rights reserved.
t
RC.