MT48LC16M16A2P-75 L Micron Technology Inc, MT48LC16M16A2P-75 L Datasheet - Page 45
MT48LC16M16A2P-75 L
Manufacturer Part Number
MT48LC16M16A2P-75 L
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC16M16A2P-75_L.pdf
(87 pages)
Specifications of MT48LC16M16A2P-75 L
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
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Mode Register
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
The mode register defines the specific mode of operation, including burst length (BL),
burst type, CAS latency (CL), operating mode, and write burst mode. The mode register
is programmed via the LOAD MODE REGISTER command and retains the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify
the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and
M10–Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and
Mn + 2 should be set to zero to select the mode register.
The mode registers must be loaded when all banks are idle, and the controller must
wait
ments will result in unspecified operation.
t
MRD before initiating the subsequent operation. Violating either of these require-
45
Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 SDRAM
© 1999 Micron Technology, Inc. All rights reserved.
Mode Register
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