N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 91

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

N25Q064 - 3 V
9.2.4
Note:
9.2.5
9.2.6
DQ0
DQ1
C
S
0
Instruction
1
2
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction code,
address and output data are all parallelized on the two pins DQ0 and DQ1.
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
Figure 46. Read OTP instruction and data-out sequence DIO-SPI
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Enable (WREN) instruction of the
Extended SPI protocol.
Figure 47. Write Enable instruction sequence DIO-SPI
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.
3
S
C
DQ0
DQ1
23 21 19 17
22 20 18 16
4
5
6
7
24-Bit Address
15 13 11 9
14 12 10 8
8
9 10 11
0
Instruction
12 13 14 15
7
6
5
4
1
3
2
2
1
0
3
16 17 18 19 20 21 22 23 24 25 26 27 28
Dual_Write_Enable
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
Dummy cycles
7
MSB
6
Data Out 1
©2010 Micron Technology, Inc. All rights reserved.
5
4
3
2
1
0
MSB
6
7
Instructions
Data Out n
4
5
2
3
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0
1