SAK-XC167CI-32F40FBB-A Infineon Technologies, SAK-XC167CI-32F40FBB-A Datasheet - Page 49

• Manufacturer Part Number: SAK-XC167CI-32F40FBB-A
• Description: Microcontrollers (MCU) 256KB FLASH 12KB RAM 2xASC 2xSSC I2C
• Manufacturer: Infineon Technologies

Specifications of SAK-XC167CI-32F40FBB-A

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 12 KB
• Interface Type: 2xASC, 2xSSC, 1xI2C
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 103
• Number Of Timers: 11
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PG-TQFP-144
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / Rohs Status: Details
• Other names: KX167CI32F40FBBAXT

3.13
The integrated TwinCAN module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
Two Full-CAN nodes share the TwinCAN module’s resources to optimize the CAN bus
traffic handling and to minimize the CPU load. The module provides up to 32 message
objects, which can be assigned to one of the CAN nodes and can be combined to FIFO-
structures. Each object provides separate masks for acceptance filtering.
The flexible combination of Full-CAN functionality and FIFO architecture reduces the
efforts to fulfill the real-time requirements of complex embedded control applications.
Improved CAN bus monitoring functionality as well as the number of message objects
permit precise and comfortable CAN bus traffic handling.
Gateway functionality allows automatic data exchange between two separate CAN bus
systems, which reduces CPU load and improves the real time behavior of the entire
system.
The bit timing for both CAN nodes is derived from the master clock and is programmable
up to a data rate of 1 Mbit/s. Each CAN node uses two pins of Port 4, Port 7, or Port 9 to
interface to an external bus transceiver. The interface pins are assigned via software.
Figure 10
Data Sheet
Decoder
Address
Interrupt
Control
Control
Clock
TwinCAN Module
TwinCAN Module Block Diagram
f
CAN
TwinCAN Module Kernel
Node A
TwinCAN Control
CAN
Message
Object
Buffer
Node B
CAN
47
RxDCA
RxDCB
TxDCA
TxDCB
Functional Description
Control
Port
XC167CI-32F
Derivatives
V1.1, 2006-08
MCB05567