ADV7177KS-REEL Analog Devices Inc, ADV7177KS-REEL Datasheet - Page 4

• Manufacturer Part Number: ADV7177KS-REEL
• Description: IC DAC VIDEO NTSC 3-CH 44MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7177KS-REEL

• Rohs Status: RoHS non-compliant
• Applications: Set-Top Boxes, TV
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 44-MQFP, 44-PQFP
• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Not Compliant

ADV7177/ADV7178
GENERAL DESCRIPTION
The ADV7177/AD7178 are integrated digital video encoders
that convert digital CCIR-601 4:2:2 8- or 16-component video
data into a standard analog baseband television signal
compatible with worldwide standards. The 4:2:2 YUV video
data is interpolated to 2× the pixel rate. The color-difference
components (UV) are quadrature modulated using a subcarrier
frequency generated by an on-chip, 32-bit digital synthesizer
(also running at 2× the pixel rate). The 2× pixel rate sampling
allows for better signal-to-noise ratio. A 32-bit DDS with a 9-bit
look-up table produces a superior subcarrier in terms of both
frequency and phase. In addition to the composite output
signal, there is the facility to output S-video (Y/C video), YUV
or RGB video.
Each analog output is capable of driving the full video-level
(34.7 mA) signal into an unbuffered, doubly terminated 75 Ω
load. With external buffering, the user has the additional option
to scale back the DAC output current to 5 mA min, thereby
significantly reducing the power dissipation of the device.
Rev. C | Page 4 of 44
The ADV7177/ADV7178 also support both PAL and NTSC
square pixel operation.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
(and can generate) HSYNC , VSYNC , and FIELD timing signals.
These timing signals can be adjusted to change pulse width and
position while the parts are in master mode. The encoder
requires a single, 2× pixel rate (27 MHz) clock for standard
operation. Alternatively, the encoder requires a 24.5454 MHz
clock for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.
The ADV7177/ADV7178 modes are set up over a 2-wire serial
bidirectional port (I
Functionally, the ADV7178 and the ADV7177 are the same
except that the ADV7178 can output the Macrovision anticopy
algorithm, and OSD is only supported on the ADV7177.
The ADV7177/ADV7178 are packaged in a 44-lead, thermally
enhanced MQFP package.
2
C-compatible) with two slave addresses.