ADV7177KS-REEL Analog Devices Inc, ADV7177KS-REEL Datasheet - Page 9

• Manufacturer Part Number: ADV7177KS-REEL
• Description: IC DAC VIDEO NTSC 3-CH 44MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7177KS-REEL

• Rohs Status: RoHS non-compliant
• Applications: Set-Top Boxes, TV
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 44-MQFP, 44-PQFP
• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Not Compliant

5 V TIMING SPECIFICATIONS
V
Table 5.
Parameter
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL AND PIXEL PORT
RESET CONTROL
INTERNAL CLOCK CONTROL
OSD TIMING
1
2
3
4
5
6
The max/min specifications are guaranteed over this range.
Temperature range T
TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤ 10 pF.
Guaranteed by characterization.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
Pixel port consists of the following:
Pixel inputs: P15–P0
Pixel controls: HSYNC , FIELD/ VSYNC , BLANK
Clock input: CLOCK
AA
SCLOCK Frequency
SCLOCK High Pulse Width, t
SCLOCK Low Pulse Width, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
Analog Output Delay
DAC Analog Output Skew
f
Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t
RESET Low Time
Clock/2 Rise Time, t
Clock/2 Fall Time, t
OSD Setup Time, t
OSD Hold Time, t
CLOCK
= 4.75 V to 5.25 V,
3, 4
4
3, 4
15
MIN
3, 5
19
12
10
9
18
5
11
to T
17
16
12
1
11
V
MAX
REF
: 0°C to 70°C.
= 1.235 V, R
14
2
7
1
6
13
3
4
8
3, 4, 6
SET
Conditions
After this period, the first clock is generated
Relevant for repeated start condition
= 300 Ω. All specifications T
Rev. C | Page 9 of 44
MIN
to T
MAX
,
2
unless otherwise noted.
Min
4.0
4.7
250
4.7
8
8
3.5
4
4
3
6
0
4.0
4.7
Typ
5
0
27
4
37
7
7
6
2
ADV7177/ADV7178
Max
100
1
300
24
Unit
kHz
µs
µs
µs
µs
ns
µs
ns
µs
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
ns
ns
ns