AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 13

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PROGRAMMABLE TIMING GENERATION
PRECISION TIMING HIGH SPEED TIMING CORE
The AD9979 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for
generating the timing for both the CCD and the AFE; the reset
gate (RG), the HL, Horizontal Driver H1 to Horizontal Driver
H4, and the SHP and SHD sample clocks. A unique architecture
makes it routine for the system designers to optimize image
quality by providing precise control over the horizontal CCD
readout and the AFE-correlated double sampling.
Timing Resolution
The Precision Timing core uses a master clock input (CLI) as a
reference. This clock is recommended to be the same as the
CCD pixel clock frequency. Figure 15 illustrates how the internal
timing core divides the master clock period into 64 steps, or
edge positions. Therefore, the edge resolution of the Precision
Timing core is t
CLI input, refer to the Applications Information section.)
POSITION
PERIOD
1 PIXEL
CLI
CLI
/64. (For more information on using the
SIGNAL
NOTES
1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (
H1, H3
H2, H4
CCD
t
CLIDLY
RG
HL
3
5
7
PROGRAMMABLE CLOCK POSITIONS:
1
2
3
4
5
6
7
8
SHP SAMPLE LOCATION.
SHD SAMPLE LOCATION.
RG RISING EDGE.
RG FALLING EDGE.
H1 RISING EDGE.
H1 FALLING EDGE.
HL RISING EDGE.
HL FALLING EDGE.
P[0]
4
Figure 16. High Speed Clock Programmable Locations (HCLKMODE = 1)
Figure 15. High Speed Clock Resolution From CLI Master Clock Input
1
6
8
P[16]
2
Rev. C | Page 13 of 56
t
CONV
P[32]
Using a 65 MHz CLI frequency, the edge resolution of the
Precision Timing core is approximately 240 ps. If a 1× system
clock is not available, it is also possible to use a 2× reference
clock, by programming the CLIDIVIDE register (Address 0x0D).
The AD9979 then internally divides the CLI frequency by 2.
High Speed Clock Programmability
Figure 16 shows how the high speed clocks, RG, HL, H1 to H4,
SHP, and SHD, are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. The HL, H1, and H2 horizontal clocks have separate
programmable rising and falling edges and polarity control. The
AD9979 provides additional HCLK mode programmability, see
Table 8.
The edge location registers are each six bits wide, allowing the
selection of all 64 edge locations. Figure 19 shows the default
timing locations for all of the high speed clock signals.
P[48]
t
CLIDLY
).
P[64] = P[0]
AD9979