AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 35

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
RECOMMENDED POWER-UP SEQUENCE
When the AD9979 is powered up, the following sequence is
recommended (refer to Figure 52 for each step).
1.
2.
3.
HORIZONTAL
SUPPLIES
CLOCKS
WRITES
POWER
(INPUT)
SERIAL
(INPUT)
(INPUT)
Turn on the power supplies for the AD9979 and apply CLI
clock. There is no required order for bringing up each supply.
Although the AD9979 contains an on-chip, power-on reset,
a software reset of the internal registers is recommended.
Write 1 to SW_RST (Address 0x10, Bit [0], which resets all
the internal registers to their default values. This bit is self-
clearing and automatically resets back to 0.
Write to the desired registers to configure high speed
timing and horizontal timing. Note that all TESTMODE
registers must be written as described in the register maps.
CLI
HD
VD
0V
1
HIGH-Z BY
DEFAULT
AD9979 SUPPLIES
2
3
4
Figure 52. Recommended Power-Up Sequence
Rev. C | Page 35 of 56
5
H2, H4
H1, H3, RG
4.
5.
6.
The next VD/HD falling edge allows register updates to occur,
including OUT_CONTROL (Address 0x11, Bit [0]), which
enables all clock outputs.
To place the part into normal power operation, write 0 to
STANDBY (Address 0x00, Bits[1:0])and REFBUF_PWRDN
(Address 0x00, Bit 2).
The Precision Timing core must be reset by writing 1 to
TGCORE_RST (Address 0x14, Bit 0). This starts the
internal timing core operation.
Write 1 to OUT_CONTROL (Address 0x11, Bit 0).
6
1H
1ST FIELD
CLOCKS ACTIVE WHEN OUT_CONTROL
REGISTER IS UPDATED AT VD/HD EDGE
1V
AD9979