AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 2

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Equivalent Input/Output Circuits ................................................ 11
Theory of Operation ...................................................................... 12
Programmable Timing Generation .............................................. 13
REVISION HISTORY
10/09—Rev. B to Rev. C
Changes to Clock Rate (CLI) Parameter, Table 1 ......................... 3
9/09—Rev. A to Rev. B
Changed SCK Falling Edge to SDATA Valid Hold Parameter to
SCK Rising Edge to SDATA Hold .................................................. 4
Changes to Individual HBLK Patterns Section .......................... 18
6/09—Rev. Sp0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Figure 2 .......................................................................... 6
Changes to Table 5 and Thermal Resistance Section ................... 7
Timing Specifications .................................................................. 4
Digital Specifications ................................................................... 5
Analog Specifications ................................................................... 6
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Precision Timing High Speed Timing Core ............................. 13
Horizontal Clamping and Blanking ......................................... 16
Rev. C | Page 2 of 56
Applications Information .............................................................. 35
3-Wire Serial Interface Timing ..................................................... 40
Outline Dimensions ....................................................................... 54
Changes to Figure 3 and Table 7 ...................................................... 8
Changes to Figure 22 ...................................................................... 16
Added GP_LINE_MODE Name, Table 16 ................................. 28
Changes to Figure 42 ...................................................................... 31
Added Example Register Settings for Power-Up Section .......... 36
Changes to Additional Restriction Section ................................. 37
Changes to Table 22, 3 V System Compatibility Section, and
Grounding and Decoupling Recommendations Section .......... 38
Changes to Table 33 ....................................................................... 51
Changes to Table 34 ....................................................................... 52
Added Exposed Paddle Notation to Outline Dimensions ........ 54
2/07—Revision Sp0: Initial Version
Complete Field—Combining H-Patterns ............................... 23
Mode Registers ........................................................................... 24
Horizontal Timing Sequence Example .................................... 26
General-Purpose Outputs (GPO) ............................................ 27
GP Look-Up Tables (LUT) ........................................................ 30
Analog Front-End Description and Operation ...................... 31
Recommended Power-Up Sequence ....................................... 35
Standby Mode Operation .......................................................... 37
CLI Frequency Change .............................................................. 37
Circuit Configuration ................................................................ 38
Grounding and Decoupling Recommendations .................... 38
Layout of Internal Registers ...................................................... 41
Updating of New Register Values ............................................. 42
Complete Register Listing ......................................................... 43
Ordering Guide .......................................................................... 54