AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 14

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
DOUTPHASEP
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN 1 PIXEL PERIOD.
2. CERTAIN POSITIONS MUST BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.
3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
H1, H3
H2, H4
H4
H1
H2
H3
SIGNAL
POSITION
1
SHD
SHP
CCD
H1 TO H4 PROGRAMMABLE LOCATIONS:
1
2
3
4
CLI
H1 RISING EDGE.
H1 FALLING EDGE.
H3 RISING EDGE.
H3 FALLING EDGE.
RG
3
H2
H1
1
H1 TO H4 PROGRAMMABLE LOCATIONS:
1
2
3
4
H1 RISING EDGE.
H1 FALLING EDGE.
H2 RISING EDGE.
H2 FALLING EDGE.
4
SHDLOC[0]
RGr[0]
H1r[0]
P[0]
2
2
4
3
t
DOUTINH
Figure 19. High Speed Timing Default Locations
RGf[16]
P[16]
Figure 17. HCLK Mode 2 Operation
Figure 18. HCLK Mode 3 Operation
Rev. C | Page 14 of 56
DATAPHASEP[32]
SHPLOC[32]
H1f[32]
P[32]
P[48]
t
S1
t
t
SHDINH
SHPINH
P[64] = P[0]