AD9979BCPZ Analog Devices Inc, AD9979BCPZ Datasheet - Page 52

• Manufacturer Part Number: AD9979BCPZ
• Description: IC PROCESSOR CCD 14BIT 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9979BCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 48mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Supply Voltage Range: 1.6V To 2V, 1.6V To 3.6V, 2.7V To 3.6V
• Operating Temperature Range: -25°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Ic Function: 14-bit CCD Signal Processor With Precision Timing Core
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9979
Address
08
09
0A
0B
0C
0D
0E
0F
1
Table 34. Field Registers
Address
00
01
02
03
X = Don’t care.
Data Bit
Content
[2:0]
[5:3]
[8:6]
[11:9]
[14:12]
[17:15]
[19:18]
[20]
[27:21]
[12:0]
[20:13]
[21]
[22]
[27:23]
[12:0]
[25:13]
[27:26]
[27:0]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
Data Bit
Content
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
Default
Value
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Default
Value
X
X
X
X
X
X
X
X
1
1
Update
Type
SCP
SCP
SCP
SCP
SCP
SCP
SCP
Update
Type
VD
VD
VD
VD
Name
HBLKALT_PAT1
HBLKALT_PAT2
HBLKALT_PAT3
HBLKALT_PAT4
HBLKALT_PAT5
HBLKALT_PAT6
HBLKMODE
TESTMODE
Unused
HBLKLEN
HBLKREP
HBLKMASK_H1
HBLKMASK_H2
Unused
HBLKSTART
HBLKEND
Unused
TESTMODE
CLPOB0_TOG1
CLPOB0_TOG2
Unused
CLPOB1_TOG1
CLPOB1_TOG2
Unused
PBLK0_TOG1
PBLK0_TOG2
Unused
PBLK1_TOG1
PBLK1_TOG2
Unused
Name
SCP0
SCP1
Unused
SCP2
SCP3
Unused
SCP4
SCP5
Unused
SCP6
SCP7
Unused
Rev. C | Page 52 of 56
Description
HBLK Pattern 1 order. Used during pixel mixing mode.
HBLK Pattern 2 order. Used during pixel mixing mode.
HBLK Pattern 3 order. Used during pixel mixing mode.
HBLK Pattern 4 order. Used during pixel mixing mode.
HBLK Pattern 5 order. Used during pixel mixing mode.
HBLK Pattern 6 order. Used during pixel mixing mode.
HBLK mode selection.
0 = normal HBLK.
1 = pixel mixing mode.
2 = special pixel mixing mode.
3 = not used.
Test operation only. Set to 0.
Set unused bits to 0.
HBLK length in HBLK alteration modes.
Number of HBLK repetitions in HBLK alternation modes.
Masking polarity for H1/H3 during HBLK.
Masking polarity for H2/H4 during HBLK.
Set unused bits to 0.
HBLK start position used in pixel mixing modes.
HBLK end position used in pixel mixing modes.
Set unused bits to 0.
Test operation only. Set to 0.
CLPOB0 Toggle Position 1.
CLPOB0 Toggle Position 2.
Set unused bits to 0.
CLPOB1 Toggle Position 1.
CLPOB1 Toggle Position 2.
Set unused bits to 0.
PBLK0 Toggle Position 1.
PBLK0 Toggle Position 2.
Set unused bits to 0.
PBLK1 Toggle Position 1.
PBLK1 Toggle Position 2.
Set unused bits to 0.
Description
Sequence Change Position 0.
Sequence Change Position 1.
Set unused bits to 0.
Sequence Change Position 2.
Sequence Change Position 3.
Set unused bits to 0.
Sequence Change Position 4.
Sequence Change Position 5.
Set unused bits to 0.
Sequence Change Position 6.
Sequence Change Position 7.
Set unused bits to 0.