FIN12ACMLX Fairchild Semiconductor, FIN12ACMLX Datasheet
FIN12ACMLX
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FIN12ACMLXTR
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FIN12ACMLX Summary of contents
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... PDA, video camera, automotive Ordering Information Operating Part Number Temperature Range FIN12ACGFX -30 to +70°C FIN12ACMLX -30 to +70°C Pb-free package per JEDEC J-STD-020B. ™ µSerDes is a trademark of Fairchild Semiconductor Corporation. © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 Description ...
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... Functional Block Diagram CKREF STROBE DP[21:22] DP[1:20] DP[23:24] CKP S1 S2 DIRI © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 PLL 0 I cksint Serializer Control + Serializer - oe Deserializer Deserializer cksint Control WORD CK Generator Control Logic DIRO Freq Direction Control Control oe Power Down Control Figure 1 ...
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... The DSO/DSI serial port pins have been arranged such that if one device is rotated 180° with respect to the other 1 device, the serial connections properly aligns without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 Number of Description of Signals ...
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... DP[7] 6 DP[8] 7 DP[9] 8 (Top View) BGA Pin Assignments 1 A DP4 B DP6 C CKP D N/C E DP8 F DP10 G DP12 N Connect © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 CKSO+ 24 CKSO- 23 DSO+/DSI- 22 DSO-/DSI+ 21 CKSI- 20 CKSI+ 19 DIRI DDS Figure 2. Terminal and Pin Assignments DP2 ...
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... X 1 © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken by the system designer to ensure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGH- impedance state prior to the DIRI signal being asserted ...
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... CKREF frequency. Similarly if the STROBE signal has significant cycle-to-cycle variation, the maximum cycle- to-cycle time needs to be factored into the selection of the CKREF frequency. © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 Serializer Operation: DIRI = 1, No CKREF A third method of serialization uses a free-running bit clock on the CKSI signal ...
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... The device receives parallel data on the rising edge of STROBE_M. 4. The device generates and transmits serialized data on the DS signals, which is source synchronous with CKSO. 5. The device generates an embedded word clock for each strobe signal. © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 From Deserializer To Serializer . ...
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... Baseband Processor Camera MASTER_CLK Interface PIXEL_CLK YUV[7:0] HSYNC VSYNC Note: V does not have to equal V DD1 Figure 6. Unidirectional 8-bit YUV Sensor with Master Clock on Base (10MHz to 40MHz Operation) © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 V 2.775 DD1 DDP DDA DDS DDS ...
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... Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. ■ Do not place test points on differential serial wires. ■ Use differential serial wires a minimum of 2cm away from the antenna. © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 For the serializer: 1. Connect CKSO of the deserializer to CKSI of the serializer. ...
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... Symbol Supply Voltage DDA DDS V Supply Voltage DDP T Operating Temperature A V Supply Noise Voltage DDA-PP © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 Parameter Parameter 10 Min. Max. Unit -0.5 +4.6 V -0.5 +4.6 V Continuous -65 +150 ° ...
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... CKSI Internal Receiver R TRM Termination Resistor CKSI Internal Receiver R TRM Termination Resistor Note : the difference in device ground levels between the CTL driver and the CTL receiver. GO © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 Test Conditions V = 3.3 ±0.30 DDP I = –2.0mA V = 2.5 ±0.20 OH DDP V = 1.8 ± ...
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... DD_SER1 DD_SER1 DDA 14:1 Dynamic Deserializer I Power Supply Current DD_DES1 DD_DES1 DDA © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 values. Typical values are measured Test Conditions All DP and Control Inputs NOCKREF DIR = 1 All DP and Control Inputs NOCKREF DIR = 0 All DP and Control Inputs ...
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... Data Valid to CKP LOW PDV t Output Rise Time (20% to 80%) ROLH t Output Fall Time (80% to 20%) ROHL © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 = 2.775V and T = 25°C. Positive current values refer to the current flowing into A ). Test Conditions CKREF = STROBE Figure 13 CKREF does not = ...
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... IN STROBE, S1, S2, DIRI C Capacitance of Parallel Port Pins DP[1:12 Capacitance of Differential I/O Signals IO-DIFF © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH DIRI HIGH-to-LOW DIRI = 0, S1( and S2(1) = LOW-to-HIGH Figure 21 DIRI = 0, S1( and S2(1) = LOW-to-HIGH ...
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... Typical values are measured 2.5V TLH 80% 20% V DIFF V = (DS+) – (DS-) DIFF DS – DS- Figure 10. CTL Output Load and Transition Times © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 DS+ DUT DS 999h values. Minimum values are measured at the minimum V DD Figure 9. “Worst Case” Serializer Test Pattern ...
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... RCOP 75% 50% CKREF 25 RCOH RCOL Setup: DIRI = “0”, CKSI and DS are valid signals. Figure 14. Deserializer Data Valid Window Time and Clock Output Parameters © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 (Continued) Data t HTC CKREF Figure 13. LVCMOS Clock Parameters t PDV ...
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... Figure 18. PLL Loss of Clock Disable Time t PLZ(HZ DS+,CKS0+ HIGHZ DS–,CKS0- Note: CKREF must be active and PLL must be stable. Figure 20. Serializer Enable and Disable Time © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 (Continued) CKSO- CKSO+ t H_DS DSO+ DSO- Figure 17. Differential Output Signal Skew ...
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... Shipping Reel Dimensions Dimensions are in millimeters. 10° maximum component rotation Sketch A (Side or Front Sectional View) Component Rotation Dia A max Tape Dia A Dim B Width Max. Min. 8 330.0 1.5 12 330.0 1.5 16 330.0 1.5 © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1 Min. ±0.1 ±0.1 ± ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the war- ranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the war- ranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.2 21 www.fairchildsemi.com ...