FIN24CMLX Fairchild Semiconductor, FIN24CMLX Datasheet - Page 5

• Manufacturer Part Number: FIN24CMLX
• Description: IC SERIALIZER/DESERIALZR 40MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN24CMLX

• Function: Serializer/Deserializer
• Data Rate: 520Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 20
• Number Of Outputs: 20
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -30°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
Control Logic Circuitry
The FIN24C has four signals that are selectable as two
unidirectional inputs and two unidirectional outputs, or as
four unidirectional inputs or four unidirectional outputs.
These are often used by applications for control signals.
The mode signals S1 and S2 determine the direction of
the DP[21:24] data signals. The 00 state provides for a
power-down state where all functionality of the device is
disabled or reset. The DIRI terminal controls the direc-
tion of the device in Modes 1 and 3. When in Mode 2, the
direction is controlled by both the DIRI and STROBE sig-
nals. Table 1 provides a complete description of the vari-
ous modes of operation. For unidirectional operation, the
DIRI terminal should be hardwired to a valid logic level
and the DIRO terminal should be left floating. For bi-
directional operation, the DIRO of the master device
should be connected to the DIRI of the slave device.
When operating in a bi-directional mode, the turn-around
functionality is dependent on the mode of the device. For
Modes 1 and 3, the device asynchronously passes and
inverts the DIRI signal through the device to the DIRO
signal. Care must be taken during design to ensure that
no contention occurs between the deserializer outputs
and the other devices on this port. Optimally the periph-
eral device driving the serializer should be in a HIGH-
impedance state prior to the DIRI signal being asserted.
Table 1. Control Logic Circuitry
Number
Mode
0
1
2
3
S2
0
0
1
1
1
S1
0
1
0
1
1
Inputs
STROBE
x
x
x
x
0
0
1
1
x
x
DIRI
0
1
0
1
0
1
0
1
0
1
DIRO (n-1)
Output
DIRO
5
1
0
1
0
1
0
1
1
0
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned around into a
deserializer and the values are overwritten.
When the device is in Mode 2 (S2 = 1, S1 = 0), the direc-
tion of operation is dependent upon both the STROBE
signal and the DIRI signal. At power-up, the mode select
signals are both LOW and the DIRO signal is the inver-
sion of the DIRI signal. After power-up, the DIRI and
STROBE signal should initially both be HIGH. When
STROBE goes LOW the device is configured as a serial-
izer and DIRO will be forced LOW. The device remains
a serializer until the DIRI signal goes LOW. When DIRI
goes LOW, the device is re-configured as a deserializer
and the DIRO signal is asserted HIGH.
When operating the SerDes in pairs, not all operating
modes are compatible. Regardless of the mode of oper-
ation, the serializer is always sending 24 bits of data and
two word boundary bits. The deserializer is always
receiving 24 bits of data and two word boundary bits. For
some modes of operation, not all of the data bits are
valid because some pins are dedicated inputs or outputs.
A value of “0” is sent in the serial stream for all invalid
data bits.
Previous
Device
State
Des
Des
Des
Des
Ser
Ser
Ser
na
na
Power-Down State. The device is
powered down and disabled
regardless of all other signals.
4-Bit Unidirectional Control Mode
DP[21:24] are outputs
4-Bit Unidirectional Control Mode
DP[21:24] are inputs
STROBE and DIRI operate as an
RS-Latch to change the state of
operation.
In general, DIRI and Strobe should
not be LOW at the same time.
2-Bit Unidirectional Control Mode
DP[21:22] are Inputs
DP[23:24] Outputs
2-Bit Unidirectional Control Mode
DP[21:22] are Inputs
DP[23:24] Outputs
Description
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