PXB4220E-V32 Infineon Technologies, PXB4220E-V32 Datasheet - Page 7
PXB4220E-V32
Manufacturer Part Number
PXB4220E-V32
Description
IC CHIPSET 8 E1/T1 LINE 256-BGA
Manufacturer
Infineon Technologies
Datasheet
1.PXB4220E-V33.pdf
(290 pages)
Specifications of PXB4220E-V32
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-BGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PXB4220E-V32
PXB4220E-V32IN
PXB4220E-V32IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PXB4220E-V32
Manufacturer:
Infineon
Quantity:
35
Company:
Part Number:
PXB4220E-V32
Manufacturer:
Infineon Technologies
Quantity:
10 000
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Table of Contents
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
7.26
7.27
7.28
7.29
7.30
7.31
7.32
7.33
7.34
7.35
7.36
7.37
7.38
7.39
7.40
7.41
7.42
7.43
7.44
7.45
7.46
Data Sheet
OAM-Counter Enable Register for AAL Ports (caal) . . . . . . . . . . . . . . . . 158
Byte-Pattern Register bp3 and bp2 (bp32) . . . . . . . . . . . . . . . . . . . . . . . 159
Byte-Pattern Register bp1 and bp0 (bp10) . . . . . . . . . . . . . . . . . . . . . . . 160
ATM Control Register (atmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
RX Idle/Unassigned Cell Control Register (rxid) . . . . . . . . . . . . . . . . . . . 162
TX Idle/Unassigned Cell Control Register (txid) . . . . . . . . . . . . . . . . . . . 163
Loopback Control Register (lpbc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Cell Fill Register for Partially Filled Cells (cfil) . . . . . . . . . . . . . . . . . . . . . 165
Interrupt Mask Register 1 (imr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Timer Enable Register (time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Cell Delineation FSM Status Register (cdfs) . . . . . . . . . . . . . . . . . . . . . . 168
Version Register (vers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Clock Monitor Register (ckmo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Interrupt Status Register 1 (isr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Extended Interrupt Status 1 Register (eis1) . . . . . . . . . . . . . . . . . . . . . . . 173
Extended Interrupt Status 2 Register (eis2) . . . . . . . . . . . . . . . . . . . . . . . 174
Extended Interrupt Status 3 Register (eis3) . . . . . . . . . . . . . . . . . . . . . . . 175
Extended Interrupt Status 4 Register (eis4) . . . . . . . . . . . . . . . . . . . . . . . 176
Interrupt Status Register 2 (isr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Operation Mode Register (opmo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
FT Clock Select Register (ftcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Cell Filter VCI Pattern 1 Register (cfvp1) . . . . . . . . . . . . . . . . . . . . . . . . . 181
Cell Filter VCI Mask 1 Register (cfvm1) . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Cell Filter VCI Pattern 2 Register (cfvp2) . . . . . . . . . . . . . . . . . . . . . . . . . 183
Cell Filter VCI Mask 2 Register (cfvm2) . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Cell Filter Payload Type Register (cfpt) . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Command Register (cmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Cell Filter Read Pointer Register (cfrp) . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Threshold Register (thrshld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
UTOPIA Configuration Register (utconf) . . . . . . . . . . . . . . . . . . . . . . . . . 189
CAS 1 Register (cas1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
CAS 2 Register (cas2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
CAS 3 Register (cas3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Threshold Register for Ports 0 and 1 (thrsp01) . . . . . . . . . . . . . . . . . . . . 194
Threshold Register for Ports 2 and 3 (thrsp23) . . . . . . . . . . . . . . . . . . . . 195
Threshold Register for Ports 4 and 5 (thrsp45) . . . . . . . . . . . . . . . . . . . . 196
Threshold Register for Ports 6 and 7 (thrsp67) . . . . . . . . . . . . . . . . . . . . 197
Extended Interrupt Status 0 Register (eis0) . . . . . . . . . . . . . . . . . . . . . . . 198
LCD Timer Register (lcdtimer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Interrupt Source Register (irs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Interrupt Mask (irm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Internal Clock Recovery Circuit Configuration Register (icrcconf) . . . . . . 202
7
PXB 4219E, PXB 4220E, PXB 4221E
IWE8, V3.4
2003-01-20
Page
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