LPC1786FBD208,551 NXP Semiconductors, LPC1786FBD208,551 Datasheet - Page 37

• Manufacturer Part Number: LPC1786FBD208,551
• Description: Processors - Application Specialized CORTEX-M3 256KB FL 80KB SRAM 4KB EE USB
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1786FBD208,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 165
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Lead Free Status / Rohs Status: Details
• Other names: 935291855551

NXP Semiconductors
Table 4.
Not all functions are available on all parts. See
LPC178X_7X
Objective data sheet
Ball
9
13
17
Row E
1
5
9
13
17
Row F
1
5
9
13
17
Row G
1
5
9
13
17
Row H
1
5
9
13
17
Row J
1
5
9
13
17
Row K
1
13
17
Row L
1
Symbol
P1[2]
P0[6]
P2[4]
P0[26]
-
-
-
P2[6]
P0[25]
-
-
-
P3[16]
P3[5]
-
-
-
P4[10]
P0[23]
-
-
-
P4[9]
P3[6]
-
-
P4[8]
VREFP
-
P0[17]
P3[7]
Pin allocation table TFBGA208
Ball Symbol
10
14
2
6
10
14
2
6
10
14
2
6
10
14
2
6
10
14
2
6
10
14
2
14
2
P1[16]
P1[7]
-
JTAG_TCK
(SWDCLK)
-
-
P2[1]
-
P3[4]
-
-
P4[11]
-
P0[24]
-
-
P5[3]
-
P3[14]
-
-
V
-
V
-
-
P0[16]
-
RTCX1
P4[22]
-
RTCX2
SS
SSA
All information provided in this document is subject to legal disclaimers.
Table 2
Rev. 2 — 27 May 2011
and
Table 7
Ball
11
15
3
7
11
15
3
7
11
15
3
7
11
15
3
7
11
15
3
7
11
15
3
15
3
(EMC pins).
Symbol
V
P2[2]
-
JTAG_TMS (SWDIO)
-
-
V
-
P3[29]
-
-
P3[17]
-
V
-
-
P4[27]
-
P3[30]
-
-
P2[8]
-
P3[31]
-
-
P4[23]
-
RSTOUT
P0[18]
-
V
DD(REG)(3V3)
SS
DD(3V3)
SS
32-bit ARM Cortex-M3 microcontroller
Ball
12
16
4
8
12
16
4
8
12
16
4
8
12
16
4
8
12
16
4
8
12
16
4
16
4
LPC178x/7x
Symbol
VSSREG
P1[13]
-
P3[3]
-
-
P2[3]
-
P5[0]
-
-
P2[5]
-
V
-
-
P2[7]
-
V
-
-
P2[9]
-
P5[1]
-
-
P0[15]
-
VSSREG
V
-
P2[30]
DDA
DD(REG)(3V3)
DD(3V3)
© NXP B.V. 2011. All rights reserved.
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