LPC1786FBD208,551 NXP Semiconductors, LPC1786FBD208,551 Datasheet - Page 84

• Manufacturer Part Number: LPC1786FBD208,551
• Description: Processors - Application Specialized CORTEX-M3 256KB FL 80KB SRAM 4KB EE USB
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1786FBD208,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 165
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Lead Free Status / Rohs Status: Details
• Other names: 935291855551

NXP Semiconductors
Table 16.
C
Values guaranteed by design.
[1]
[2]
Table 17.
C
Values guaranteed by design.
LPC178X_7X
Objective data sheet
Symbol
t
t
t
t
t
Read cycle parameters
t
t
Write cycle parameters
t
t
Symbol
Common to read and write cycles
t
t
t
t
t
t
t
t
t
t
t
t
Read cycle parameters
t
t
Write cycle parameters
t
t
h(W)
d(GV)
h(G)
d(AV)
h(A)
su(D)
h(D)
d(QV)
h(Q)
d(SV)
h(S)
d(RASV)
h(RAS)
d(CASV)
h(CAS)
d(WV)
h(W)
d(GV)
h(G)
d(AV)
h(A)
su(D)
h(D)
d(QV)
h(Q)
L
L
= 30 pF, T
= 30 pF, T
The data input set-up time has to be selected with the following margin:
t
The data input hold time has to be selected with the following margin:
t
su(D)
h(D)
+ sdram access time  board delay time  delay time of feedback clock  0.
+ delay time of feedback clock  sdram access time  board delay time  0.
Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00
Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01
amb
amb
Parameter
write hold time
output enable valid delay time
output enable hold time
address valid delay time
address hold time
data input set-up time
data input hold time
data output valid delay time
data output hold time
Parameter
chip select valid delay time
chip select hold time
row address strobe valid delay time
row address strobe hold time
column address strobe valid delay time
column address strobe hold time
write valid delay time
write hold time
output enable valid delay time
output enable hold time
address valid delay time
address hold time
data input set-up time
data input hold time
data output valid delay time
data output hold time
=
=


40
40


C to 85
C to 85


C, V
C, V
DD(REG)(3V3)
DD(REG)(3V3)
All information provided in this document is subject to legal disclaimers.
= 3.0 V to 3.6 V. All programmable delays EMCDLYCTL are bypassed.
= 3.0 V to 3.6 V. All programmable delays EMCDLYCTL are bypassed.
Rev. 2 — 27 May 2011
Conditions
Conditions
32-bit ARM Cortex-M3 microcontroller
Min
1.6
-
-
3.4
1.1
5.3
3.7
3.9
0.2
Min
2.7
1.0
2.7
1.1
2.7
1.2
3.2
1.6
-
-
3.3
1.0
5.3
3.7
3.3
0.2
-
4.1
-
Typ
2.4
-
5.0
1.7
3.8
4.3
5.8
0.6
Typ
4.1
1.6
4.1
1.7
1.8
4.8
2.3
-
4.9
1.6
3.8
4.3
4.9
0.5
LPC178x/7x
© NXP B.V. 2011. All rights reserved.
Max
4.2
-
-
7.4
3.0
1.5
5.2
8.7
1.6
Max
6.0
3.1
6.0
3.3
6.1
3.3
7.1
4.2
-
-
7.3
2.8
1.5
5.2
7.3
1.6
…continued
84 of 117
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns