LPC1786FBD208,551 NXP Semiconductors, LPC1786FBD208,551 Datasheet - Page 85

• Manufacturer Part Number: LPC1786FBD208,551
• Description: Processors - Application Specialized CORTEX-M3 256KB FL 80KB SRAM 4KB EE USB
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1786FBD208,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 165
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Lead Free Status / Rohs Status: Details
• Other names: 935291855551

NXP Semiconductors
[1]
[2]
LPC178X_7X
Objective data sheet
Fig 19. Dynamic external memory interface signal timing (read access)
The data input set-up time has to be selected with the following margin:
t
The data input hold time has to be selected with the following margin:
t
su(D)
h(D)
+ sdram access time - board delay time - delay time of feedback clock  0.
+ delay time of feedback clock  sdram access time  board delay time  0.
CLKOUT
DYCS
DQM
RAS
CAS
WE
D
A
Table 18.
C
[1]
Symbol Parameter Conditions
t
d
L
t
t
t
d(CS)
d(RAS)
d(A)
= 30 pF, T
The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All
delay times are incremental delays for each element starting from delay block 0. See the LPC178x/7x user
manual for details.
delay time
Dynamic characteristics: Dynamic external memory interface programmable
clock delays
amb
t
t
t
h(CS)
h(RAS)
h(A)
=
All information provided in this document is subject to legal disclaimers.

40

Programmable delay block 0
(CMDDLY or CLKOUTnDLY bit 0 = 1)
Programmable delay block 1
(CMDDLY or CLKOUTnDLY bit 1 = 1)
Programmable delay block 2
(CMDDLY or CLKOUTnDLY bit 2 = 1)
Programmable delay block 3
(CMDDLY or CLKOUTnDLY bit 3 = 1)
Programmable delay block 4
(CMDDLY or CLKOUTnDLY bit 4 = 1)
C to 85
Rev. 2 — 27 May 2011
t
d(CAS)

C, V
DD(REG)(3V3)
t
h(CAS)
= 3.0 V to 3.6 V.Values guaranteed by design.
32-bit ARM Cortex-M3 microcontroller
t
d(DQM)
t
su(D)
t
h(D)
[1]
[1]
[1]
[1]
[1]
Min
0.06 0.09
0.21 0.32
0.54 0.82
1.17 1.76
2.43 3.66
LPC178x/7x
Typ
© NXP B.V. 2011. All rights reserved.
002aag205
t
h(DQM)
Max
0.15
0.53
1.34
2.87
5.97
85 of 117
ns
ns
ns
ns
ns
Unit