SC16IS850LIBS,128 NXP Semiconductors, SC16IS850LIBS,128 Datasheet
SC16IS850LIBS,128
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SC16IS850LIBS,128 Summary of contents
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SC16IS850L Single UART with I and receive FIFOs, IrDA SIR built-in support Rev. 1 — 22 July 2011 1. General description The SC16IS850L is a slave I UART. It offers data rates Mbit/s and guarantees low operating ...
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... NXP Semiconductors Transmitter and receiver can be enabled/disabled independent of each other Receive and Transmit FIFO levels Programmable special character detection Fully programmable character formatting 5-bit, 6-bit, 7-bit or 8-bit character Even, odd parity Line break generation and detection ...
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... NXP Semiconductors 5. Block diagram Fig 1. Fig 2. SC16IS850L Product data sheet SC16IS850L RESET SCL SDA C-BUS A1 IRQ 1 kΩ (1 I2C/SPI XTAL1 XTAL2 Block diagram of SC16IS850L I SC16IS850L RESET SCLK CS SO SPI SI IRQ 1 kΩ (1 I2C/SPI XTAL1 Block diagram of SC16IS850L SPI interface All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning terminal 1 index area I2C/SPI SCL/SCLK Fig 3. 6.2 Pin description Table 2. Symbol CTS TX RX RESET XTAL1 XTAL2 V DD SC16IS850L Product data sheet CTS 2 17 RESET 3 16 RTS SC16IS850LIBS IRQ CS/ S1/A1 n.c. 002aaf745 Transparent top view Pin configuration for HVQFN24 ...
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... NXP Semiconductors Table 2. Symbol V SS I2C/SPI CS/A0 SI/A1 SO SCL/SCLK SDA IRQ SC16IS850L Product data sheet Pin description …continued Pin Type HVQFN24 TSSOP24 [ I All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Description Power ground ...
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... NXP Semiconductors Table 2. Symbol RTS DSR CD RI DTR n.c. [1] HVQFN24 package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region ...
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... NXP Semiconductors 7. Functional description Please refer to The SC16IS850L provides serial asynchronous receive data synchronization, serial-to-serial data conversions for both the transmitter and receiver sections. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data character ...
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... NXP Semiconductors 7.2 Internal registers The SC16IS850L provides a set of 25 internal registers for monitoring and controlling the functions of the UART. These registers are shown in Table General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, EFCR, SPR Baud rate register set (DLL/DLM Second special register set (TXLVLCNT/RXLVLCNT) ...
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... NXP Semiconductors 7.3 FIFO operation 7.3.1 32-byte FIFO mode When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the ‘first extra feature register set’ are empty (0x00) the transmit and receive trigger levels are set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to the SC16C650B (see transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]) ...
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... NXP Semiconductors With the automatic hardware flow control function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The RTS (or DTR) pin will not be forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level. ...
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... NXP Semiconductors the receive FIFO passes the programmed trigger level. To clear this condition, the SC16IS850L will transmit the programmed Xon1/Xon2 characters as soon as the number of characters in the receive FIFO drops below the programmed trigger level. 7.6 Special character detect A special character detect feature is provided to detect an 8-bit character when EFR[5] is set ...
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... NXP Semiconductors 7.8 Programmable baud rate generator The SC16IS850L UART contains a programmable rational baud rate generator that takes any clock input and divides divisor in the range between 1 and (2 SC16IS850L offers the capability of dividing the input frequency by rational divisor. The fractional part of the divisor is controlled by the CLKPRES register in the ‘first extra feature register set’ ...
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... NXP Semiconductors Fig 6. Fig 7. Table 5. Output baud rate (bit/ 110 150 300 600 1.2 k 2.4 k 3.6 k 4.8 k 7.2 k 9.6 k 19.2 k 38.4 k 57.6 k 115.2 k SC16IS850L Product data sheet XTAL1 XTAL2 XTAL1 X1 1.8432 MHz Crystal oscillator connection 100 pF f XTAL1 If f frequency is greater than 50 MHz, then a DC blocking capacitor is required. ...
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... NXP Semiconductors 7.9 Loopback mode The internal loopback capability allows on-board diagnostics. In the Loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally (see Figure In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally ...
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... NXP Semiconductors SC16IS850L REGISTER I2C/SPI SELECT CS LOGIC INTERRUPT IRQ CONTROL LOGIC Fig 8. Internal Loopback mode diagram SC16IS850L Product data sheet TRANSMIT FIFO REGISTERS FLOW CONTROL LOGIC RECEIVE FIFO REGISTERS FLOW CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 7.10 Sleep mode Sleep mode is an enhanced feature of the SC16IS850L UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] bit is set. 7.10.1 Conditions to enter Sleep mode Sleep mode is entered when: • Modem input pins are not toggling. ...
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... NXP Semiconductors 7.11 RS-485 features 7.11.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR[1 hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. AFCR2[4] will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTS pin ...
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... NXP Semiconductors 7.11.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the address byte) the receiver will try to detect an address byte that matches the programmed character in the Xoff2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the Xoff2 register, the receiver will discard these data ...
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Table 6. SC16IS850L internal registers [ Register Default Bit 7 [2] General register set RHR 0xXX bit THR 0xXX bit IER 0x00 CTS [3] interrupt 0 ...
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Table 6. SC16IS850L internal registers …continued [ Register Default Bit 7 [5] Enhanced feature register set EFR 0x00 Auto CTS Xon1 0x00 bit Xon2 0x00 bit 15 ...
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... NXP Semiconductors 8.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data byte [D7:D0] to the transmit FIFO ...
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... NXP Semiconductors Table 7. Bit Symbol Description 1 IER[1] 0 IER[0] 8.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • ...
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... NXP Semiconductors 8.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO trigger levels. 8.3.1 FIFO mode Table 8. Bit 7:6 5 [1] For 128-byte FIFO mode, refer to [2] For 128-byte FIFO mode, refer to Table 9 ...
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... NXP Semiconductors Table 10. FCR[ [1] When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see 8.4 Interrupt Status Register (ISR) The SC16IS850L provides six levels of prioritized interrupts to minimize external software interaction ...
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... NXP Semiconductors Table 12. Bit 0 8.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 13. Bit 7 6 5:3 ...
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... NXP Semiconductors Table 16. LCR[ 8.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 17. Bit SC16IS850L Product data sheet LCR[1:0] word length LCR[0] Word length (bits Modem Control Register bits description Symbol Description MCR[7] ...
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... NXP Semiconductors 8.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16IS850L and the CPU. Table 18. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16IS850L Product data sheet Line Status Register bits description Description FIFO data error ...
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... NXP Semiconductors 8.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16IS850L is connected. Four bits of this register are used to indicate the changed information ...
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... NXP Semiconductors 8.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: ‘first extra feature register set’, ‘second extra feature register set’, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). ...
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... NXP Semiconductors 8.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers ...
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... NXP Semiconductors Table 22. Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 8.15 Transmit Interrupt Level Register (TXINTLVL) This 8-bit register is used to store the transmit FIFO trigger levels used for interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1. ...
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... NXP Semiconductors [1] For 32-byte FIFO mode, refer to 8.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. register bit settings; see Table 25. Bit 7:0 [1] For 32-byte FIFO mode, refer to 8 ...
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... NXP Semiconductors 8.20 RS-485 Turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode RTS or DTR pin is used to control the direction of the line driver, after the last bit of data has been shifted out of the transmit shift register the UART will count down the value in this register ...
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... NXP Semiconductors 8.22 Advanced Feature Control Register 1 (AFCR1) Table 30. Bit 7 [1] It takes 4 XTAL1 clocks to reset the device. SC16IS850L Product data sheet Advanced Feature Control Register 1 register bits description Symbol Description AFCR1[7:5] reserved AFCR1[4] Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive. logic input is level-sensitive pin is LOW, the UART will not go to sleep ...
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... NXP Semiconductors 8.23 SC16IS850L external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 31. Table 31. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR Xon1 ...
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... NXP Semiconductors C-bus operation The two lines of the I lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy. Each device is recognized by a unique address whether microcomputer, LCD driver, memory or keyboard interface and can operate as either a transmitter or receiver, depending on the function of the device ...
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... NXP Semiconductors SDA MSB SCL 0 S START condition Fig 11. Data transfer on the I data output by transmitter data output by receiver SCL from master START condition Fig 12. Acknowledge on the I A slave receiver must generate an acknowledge after the reception of each byte, and a master must generate one after the reception of each byte clocked out of the slave transmitter. There are two exceptions to the ‘ ...
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... NXP Semiconductors An address on the network is seven bits long, appearing as the most significant bits of the address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete data transfer, comprised of an address byte indicating a ‘ ...
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... NXP Semiconductors master write: S SLAVE ADDRESS START condition master read: S SLAVE ADDRESS START condition combined S SLAVE ADDRESS formats: START condition read or 2 Fig 14. I C-bus data formats 9.3 Addressing Before any data is transmitted or received, the master must send the address of the receiver via the SDA line ...
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... NXP Semiconductors locations for a multi-byte transfer. A subaddress is an 8-bit byte. Unlike the device address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus it must be followed by an acknowledge. Table 34 not used, bits [5:3] are used to select one of the device’s internal registers, and bits [7:6] are not used ...
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... NXP Semiconductors Table 34. Bit 7:6 5:3 2:0 SC16IS850L Product data sheet 2 Register address byte (I C) Name Function - not used A[2:0] UART’s internal register select - not used; set to 0 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 ...
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SCLK CH0 X SI R/W A0 CH1 R A[2:0] = register address; CH1 = 0, CH0 = don’t care a. Register write SCLK CH1 ...
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... NXP Semiconductors Table 35. Bit 7 6 5:3 2:0 11. Limiting values Table 36. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg P /pack tot [ 12. Static characteristics Table 37. Static characteristics + 1. 1.95 V; unless otherwise specified. amb DD Symbol Parameter Supplies ...
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... NXP Semiconductors Table 37. Static characteristics + 1. 1.95 V; unless otherwise specified. amb DD Symbol Parameter 2 I C-bus input/output SDA V HIGH-level input voltage IH V LOW-level input voltage IL V LOW-level output voltage OL I LOW-level input leakage current LIL I HIGH-level input leakage current LIH ...
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... NXP Semiconductors 13. Dynamic characteristics 2 Table 38. I C-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; + 1. 1.95 V, and refer to V amb pF, except SDA output load = 400 pF. Symbol Parameter ...
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... NXP Semiconductors RESET Fig 18. SCL delay after reset START protocol condition (S) t SU;STA SCL t BUF SDA Rise and fall times refer Fig 19. I C-bus timing diagram SLAVE ADDRESS SDA IRQ MODEM pin Fig 20. Modem input pin interrupt SC16IS850L Product data sheet ...
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... NXP Semiconductors RX IRQ Fig 21. Receive interrupt SLAVE ADDRESS SDA IRQ Fig 22. Receive interrupt clear SLAVE ADDRESS SDA IRQ Fig 23. Transmit interrupt clear SC16IS850L Product data sheet start bit RHR SLAVE ADDRESS THR REGISTER All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Table 39. f dynamic characteristics XTAL1 + 1. 1.95 V. amb DD Symbol Parameter t pulse width HIGH WH t pulse width LOW WL f frequency on pin XTAL1 XTAL1 [1] Applies to external clock, crystal oscillator max. 24 MHz. 1 -------------- - f = [2] XTAL1 t w clk external clock 1 -------------- - ...
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... NXP Semiconductors CS t CSH t CSS SCLK Fig 25. Detailed SPI-bus timing CS SCLK R/W DTR R A[3:0] = MCR (0x04); CH1 = 0; CH0 = 0 Fig 26. SPI write MCR to DTR output switch CS SCLK R/W SO IRQ R A[3:0] = THR (0x00); CH1 = 0; CH0 = 0 Fig 27. SPI write THR to clear TX INT SC16IS850L Product data sheet ...
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... NXP Semiconductors CS SCLK R/W SO IRQ R A[3:0] = MSR (0x06); CH1 = 0; CH0 = 0 Fig 28. Read MSR to clear modem INT CS SCLK R/W SO IRQ R A[3:0] = RHR (0x00); CH1 = 0; CH0 = 0 Fig 29. Read RHR to clear RX INT SC16IS850L Product data sheet A1 A0 CH1 CH0 d12 A1 A0 CH1 CH0 X D7 ...
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... NXP Semiconductors IrDA TX data Fig 30. Infrared transmit timing IrDA RX data RX data Fig 31. Infrared receive timing SC16IS850L Product data sheet start TX data bit time bit time start All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I ...
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... NXP Semiconductors 14. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 34. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 43. Acronym CMOS CPU FIFO 2 I C-bus IrDA LSB MSB SIR SPI UART SC16IS850L Product data sheet ...
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... NXP Semiconductors 17. Revision history Table 44. Revision history Document ID Release date SC16IS850L v.1 20110722 SC16IS850L Product data sheet Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: SC16IS850L Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2.2 I C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Extended mode (128-byte FIFO ...