SC16IS850LIBS,128 NXP Semiconductors, SC16IS850LIBS,128 Datasheet - Page 4

• Manufacturer Part Number: SC16IS850LIBS,128
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIBS,128

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
6. Pinning information
SC16IS850L
Product data sheet
6.1 Pinning
6.2 Pin description
Table 2.
Symbol
CTS
TX
RX
RESET
XTAL2
V
XTAL1
Fig 3.
DD
index area
terminal 1
SCL/SCLK
I2C/SPI
n.c.
SO
RX
TX
Pin configuration for HVQFN24
Pin description
Pin
HVQFN24
18
5
4
17
7
8
22
1
2
3
4
5
6
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Transparent top view
SC16IS850LIBS
Rev. 1 — 22 July 2011
TSSOP24
16
2
1
15
4
5
20
18
17
16
15
14
13
002aaf745
CTS
RESET
RTS
IRQ
CS/A0
S1/A1
Type
I
O
I
I
I
O
-
Description
UART clear to send (active LOW). A logic 0
(LOW) on the CTS pin indicates the modem or
data set is ready to accept transmit data from the
SC16IS850L. Status can be tested by reading
MSR[4]. This pin only affect the transmit and
receive operations when Auto-CTS function is
enabled via the Enhanced Feature Register
EFR[7] for hardware flow control operation.
UART transmitter output. During the local
Loopback mode, the TX output pin is disabled
and TX data is internally connected to the UART
RX input.
UART receiver input. During the local Loopback
mode, the RX input pin is disabled and TX data
is connected to the UART RX input internally.
Device hardware reset (active LOW).
Crystal input or external clock input. Functions as
a crystal input or as an external clock input. A
crystal can be connected between XTAL1 and
XTAL2 to form an internal oscillator circuit (see
Figure
connected to this pin.
Crystal output or clock output. (See also XTAL1.)
XTAL2 is used as a crystal oscillator output.
Power supply.
Fig 4.
XTAL1
XTAL2
Single UART with I
CS/A0
SI/A1
DTR
V
IRQ
n.c.
n.c.
n.c.
RX
TX
SS
6). Alternatively, an external clock can be
10
11
12
1
2
3
4
5
6
7
8
9
Pin configuration for TSSOP24
SC16IS850LIPW
SC16IS850L
2
C-bus/SPI interface
002aaf746
© NXP B.V. 2011. All rights reserved.
24
23
22
21
20
19
18
17
16
15
14
13
SCL/SCLK
I2C/SPI
SO
SDA
V
RI
CD
DSR
CTS
RESET
n.c.
RTS
DD
4 of 60