SC16IS850LIBS,128 NXP Semiconductors, SC16IS850LIBS,128 Datasheet - Page 5

• Manufacturer Part Number: SC16IS850LIBS,128
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIBS,128

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SC16IS850L
Product data sheet
Table 2.
Symbol
V
I2C/SPI
CS/A0
SI/A1
SO
SCL/SCLK
SDA
IRQ
SS
Pin description
Pin
HVQFN24
9
2
14
13
1
3
24
15
[1]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2011
TSSOP24
6
23
11
10
22
24
21
12
…continued
I
Type
-
I
I
O
I
I/O
O
Description
Power ground.
I
I
logic HIGH. SPI interface is selected if this pin is
at logic LOW.
This pin has an internal pull-up resistor, and can
be left unconnected if I
SPI chip select or I
A0.
If SPI configuration is selected by I2C/SPI pin,
this pin is the SPI chip select pin (Schmitt-trigger,
active LOW). If I
by I2C/SPI pin, this pin along with A1 pin allows
user to change the device’s base address.
For I
refer to
SPI data input pin or I
select A1.
If SPI configuration is selected by I2C/SPI pin,
this is the SPI data input pin. If I
configuration is selected by I2C/SPI pin, this pin
along with A0 pin allows user to change the
device’s base address.
For I
refer to
SPI data output pin. If SPI configuration is
selected by I2C/SPI pin, this is a 3-stateable
output pin. If I
I2C/SPI pin, this pin function is undefined and
must be left as n.c. (not connected).
I
I
configuration is selected by I2C/SPI pin. If SPI
configuration is selected then this pin is an
undefined pin and must be connected to V
Interrupt (open-drain, active LOW).
Interrupt is enabled when interrupt sources are
enabled in the Interrupt Enable Register (IER).
Interrupt conditions include: change of state of
the input pins, receiver errors, available receiver
buffer data, available transmit buffer space, or
when a modem status flag is detected.
An external 10 k resistor must be connected
between this pin and V
2
2
2
2
C-bus or SPI interface select.
C-bus interface is selected if this pin is at
C-bus or SPI input clock.
C-bus data input/output, open-drain if I
Single UART with I
2
2
C-bus slave address configuration, please
C-bus slave address configuration, please
Table
Table 33
2
33.
C-bus configuration is selected by
2
C-bus configuration is selected
2
C-bus device address select
SC16IS850L
2
C-bus device address
2
DD
C-bus mode is selected.
.
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
2
C-bus
2
C-bus
SS
5 of 60
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