SC16IS850LIBS,128 NXP Semiconductors, SC16IS850LIBS,128 Datasheet - Page 36

• Manufacturer Part Number: SC16IS850LIBS,128
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIBS,128

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
9. I
SC16IS850L
Product data sheet
2
C-bus operation
9.1 Data transfers
The two lines of the I
lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the
bus is not busy. Each device is recognized by a unique address whether it is a
microcomputer, LCD driver, memory or keyboard interface and can operate as either a
transmitter or receiver, depending on the function of the device. A device generating a
message or data is a transmitter, and a device receiving the message or data is a
receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a
microcontroller or a memory can both transmit and receive data.
One data bit is transferred during each clock pulse (see
line must remain stable during the HIGH period of the clock pulse in order to be valid.
Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW
transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START
condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP
condition (see
and free again at a certain time interval after the STOP condition. The START and STOP
conditions are always generated by the master.
The number of data bytes transferred between the START and STOP condition from
transmitter to receiver is not limited. Each byte, which must be eight bits long, is
transferred serially with the most significant bit first, and is followed by an acknowledge bit
(see
master. The device that acknowledges has to pull down the SDA line during the
acknowledge clock pulse, while the transmitting device releases this pulse (see
Figure
Fig 9.
Fig 10. START and STOP conditions
Figure
12).
SDA
SCL
Bit transfer on the I
11). The clock pulse related to the acknowledge bit is generated by the
Figure
All information provided in this document is subject to legal disclaimers.
START condition
SDA
SCL
2
C-bus are a serial data line (SDA) and a serial clock line (SCL). Both
10). The bus is considered to be busy after the START condition
S
Rev. 1 — 22 July 2011
2
C-bus
data valid
data line
stable;
allowed
change
of data
Single UART with I
Figure
9). The data on the SDA
SC16IS850L
STOP condition
mba607
2
C-bus/SPI interface
P
© NXP B.V. 2011. All rights reserved.
mba608
36 of 60