SC16IS850LIBS,128 NXP Semiconductors, SC16IS850LIBS,128 Datasheet - Page 21

• Manufacturer Part Number: SC16IS850LIBS,128
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIBS,128

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SC16IS850L
Product data sheet
8.1 Transmit (THR) and Receive (RHR) Holding Registers
8.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data byte [D7:D0] to the
transmit FIFO. The THR empty flag in the LSR will be set to a logic 1 when the transmit
FIFO is empty or when data is transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16IS850L
receive FIFO by reading the RHR. The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start bit, an internal receiver counter
starts counting clocks at the 16 clock rate. After 7
shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a
logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INT output pin.
Table 7.
Bit
6
5
4
3
2
7
Symbol Description
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
IER[2]
Interrupt Enable Register bits description
All information provided in this document is subject to legal disclaimers.
CTS interrupt.
RTS interrupt.
Xoff interrupt.
Sleep mode.
Modem Status Interrupt. This interrupt will be issued whenever there is a modem
status change as reflected in MSR[3:0].
Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16IS850L issues an interrupt when
the CTS pin transitions from a logic 0 to a logic 1.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16IS850L issues an interrupt when
the RTS pin transitions from a logic 0 to a logic 1.
logic 0 = disable the software flow control, receive Xoff interrupt (normal default
condition)
logic 1 = enable the receive Xoff interrupt
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
logic 0 = disable the modem status register interrupt (normal default condition)
logic 1 = enable the modem status register interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
Rev. 1 — 22 July 2011
Single UART with I
1
⁄
2
clocks, the start bit time should be
SC16IS850L
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
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